Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.

Abstract: A storage access request to access a solid state drive (SSD) is received. A storage access timer is set with a time duration, where the time duration is based on a desired performance of the SSD. A non-volatile memory command associated with the storage access request is sent to non-volatile memory. The storage access timer is started. A determination is made whether the non-volatile memory completed execution of the non-volatile memory command after the storage access timer indicates that the time duration elapsed. An indication that the storage access request is complete is sent to a host if the non-volatile memory completed execution of the non-volatile memory command. Alternatively, the storage access timer is reset with the time duration if the non-volatile memory has not completed execution of the non-volatile memory command.

Abstract: A memory system may include a cache memory, a nonvolatile memory, a write back wait queue, and a controller. To evict an eviction cache entry including a target transaction ID from the memory cache to the nonvolatile memory, the controller performs write back operations on cache entries respectively corresponding to waiting entries at a head of the write back wait queue until a waiting entry including the target transaction ID arrives at the head of the write back wait queue, and then performs a write back operation on the eviction cache entry.

Abstract: A method comprising: receiving a request to write data at a virtual location; writing the data to a physical location on a persistent storage device; and recording a mapping from the virtual location to the physical location; wherein the physical location corresponds to a next free block in a sequence of blocks on the persistent storage device.

Abstract: Data processing techniques comprise, in response to determining that a storage unit storing first data blocks is damaged, determining storage units associated with the storage unit, and obtaining second data blocks from the storage units, where the second data blocks and the first data blocks are generated by applying to data an error correction code in a first format. The method further comprises recovering the first data blocks based on the second data blocks. In addition, the method comprises generating error correction blocks by applying an error correction code in a second format to the recovered first data blocks, where the second format is different from the first format. The above techniques can reduce input/output operations and shortens the recovery time of data blocks, and further can reduce the risk of data loss even in an extremely bad situation.

Abstract: Techniques perform resource configuration. The techniques involve determining, for a resource quota checking task for a file system on a storage system, a current workload of the storage system; in response to the workload exceeding a predetermined upper threshold, performing the resource quota checking task with a first number of processes; and in response to the workload being below a predetermined lower threshold, performing the resource quota checking task with a second number of processes, the second number being greater than the first number.

Abstract: A host server in a server cluster has a memory allocator that creates a dedicated host application data cache in storage class memory. A background routine destages host application data from the dedicated cache in accordance with a destaging plan. For example, a newly written extent may be destaged based on aging. All extents may be flushed from the dedicated cache following host server reboot. All extents associated with a particular production volume may be flushed from the dedicated cache in response to a sync message from a storage array.

Abstract: A controller may include a memory configured to store a map update list in which information of map segments whose mapping information is to be updated is registered The controller may also include an unmap module. The unmap module may, in response to receiving an unmap command, generate a list information bitmap indicating map segments which are already registered in the map update list, check, using the generate list information bitmap, whether one or more unmap target map segments corresponding to the unmap command overlap the map segments registered in the map update list, using the generate list information bitmap, and selectively register the one or more unmap target map segments into the map update list according to the check result.

Abstract: A method and apparatus is disclosed for transferring data from a first processor core to a second processor core. The first processor core executes a stash instruction having a first operand associated with a data address of the data. A second processor core is determined to be a stash target for a stash message, based on the data address or a second operand. A stash message is sent to the second processor core, notifying the second processor core of the written data. Responsive to receiving the stash message, the second processor core can opt to store the data in its cache. The data may be included in the stash message or retrieved in response to a read request by the second processing core. The second processor core may be determined by prediction based, at least in part, on monitored data transactions.

Abstract: This invention relates to the use of dynamic MPU regions to enhance the security and ease of development of multitasking embedded and similar systems.

Abstract: An information processing system includes a CPU that is configured to output an address and a writing instruction signal instructing to write data to the address or a reading instruction signal instructing to read data from the address, to a selector, the selector that is configured by hardware such that an output destination of data input from the CPU is determined according to the address, the writing instruction signal, and the reading instruction signal, a volatile memory that is configured to store data including snapshot image information and initial setting data for a non-standard device including a register when the information processing system is started, on the basis of a signal output from the selector, and the register that has the same address as an address of a memory region of the volatile memory storing the initial setting data.

Abstract: Solutions for processing a redundant array of storage drives receiving a rebuilding request of a redundant array of storage drives. The redundant array has a first storage drive to be replaced. In response to no spare storage drive being available to logically replace the first storage drive, a second storage drive is identified, which is a source storage drive of a disk balance process being performed. A rebuilding of the redundant array is initiated by reconstructing data of the first storage drive on the second storage drive during the disk balance process.

Abstract: Described herein are systems and techniques to efficiently cache data for streaming applications. A cache can be organized to include multiple cache segments, and each cache segment can include multiple cache blocks. A cache entry can be created for streaming data, and the streaming data can be streamed directly into a first cache block. When the first cache block is full, a next cache block can be identified, in a same cache segment or in a new cache segment. The streaming data can be streamed directly into the next cache block, and into any further cache blocks as needed.

Abstract: A method and apparatus for performing mapping information management regarding a RAID are provided. The method includes: writing data into a data region of the RAID in a redirect-on-write (ROW) manner, and recording mapping information between logical addresses of the data and protected-access-unit addresses (p-addresses) of protected access units in the data region into a logical-address-to-p-address (L2p) table within a table region of the RAID; when partial data of the data is updated, maintaining an updating list including a set of L2p table entries for the partial data in a RAM, and maintaining a recovery log corresponding to the updating list in a log region of the RAID, for power failure recovery; and according to the updating list, detecting whether a number of same-location L2p table entries in the set of L2p table entries reaches a predetermined threshold, to selectively update the L2p table with the same-location L2p table entries.

Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

Abstract: In an approach to intelligently choosing transport channels across protocols by drive type, one or more transport channels on a host are detected. One or more storage drive tiers on a target are detected. The one or more transport channels are mapped to the one or more storage drive tiers, based on performance. A transfer of a data between a host and the target is completed, using each transport channel and each storage drive tier.

Abstract: An electronic device may include: a controller; a non-transitory computer-readable storage medium configured to store operation codes for causing the controller to perform operations; and a buffer configured to temporarily store data between a host device and the non-transitory computer-readable storage medium through control of the controller, wherein the operations comprise monitoring a foreground buffer usage rate of the buffer in response to a command of the host device and adjusting a foreground buffer capacity for the command in the buffer, based on the monitored foreground buffer usage rate.

Abstract: A storage device includes a controller and a memory. In response to a request of a host, the controller generates: (A) a first list as a result of counting: (1) the number of first page numbers included in a first range among page numbers included in a logical address received from the host and (2) the number of second page numbers included in a second range not overlapping the first range, (B) generates a second list as a result of respectively grouping the first page numbers and the second page numbers based on the first list, and (C) translates the logical address to a physical address based on the second list and the first map data. The memory stores the first map data to be provided to the controller. The first map data matches the first page numbers and the second page numbers with respective physical addresses.

Abstract: A high-temperature protection method for a solid state drive (SSD) and an implementation device thereof are provided. The device includes a temperature measurement circuit, a host communication interface, a SSD main controller and NAND Flash storage medium chips, wherein the SSD main controller is for controlling data transmission and command interaction between a host and the NAND Flash storage medium chips, including a SATA/PCIe (serial advanced technology attachment/peripheral component interconnect express) physical controller, a high-temperature control manager, a main controller core, a RAM (random access memory) and a NAND Flash controller.

Abstract: A tag match determination unit determines, in response to an acquisition request for predetermined data, whether predetermined data is present in a primary cache. When the predetermined data is not present in the primary cache, the move-in buffer outputs the acquisition request for the predetermined data to a secondary cache management unit or the storage device and holds determination purpose information based on state information on a predetermined area that stores therein the predetermined data. A storage processing unit determines, when an acquired response from the secondary cache management unit or the storage device is a predetermined type, based on the determination purpose information, whether or not to acquire the state information stored in the primary cache; invalidates the predetermined area when it is determined not to acquire the state information; and stores, in the predetermined area, the predetermined data included in the response.