Abstract: A power management method and apparatus, and a power supply system are provided. The method includes: obtaining a power demand value of each module and a rated output power of each power supply unit (PSU) in a communication equipment; calculating the obtained power demand value of each module to acquire a total power demand value of the modules; and adjusting, according to the calculated total power demand value of the modules and the obtained rated output power of each PSU, the current number of the PSUs actually turned on in the communication equipment.

Abstract: A clock generation circuit generates clock signals of a requested frequency and relative phase by dividing a reference clock signal by counting reference clock signal pulses in a counter circuit. The clock generation circuit changes the frequency, and optionally also the phase, of an output clock signal upon request, without generating glitches or missing pulses. The clock generation circuit does not alter the frequency of the output clock signal until a phase pulse associated with the requested phase is asserted, and the counter circuit is in a predetermined state, such as a reset state.

Abstract: A system can include a processor; memory operatively coupled to the processor; a chipset operatively coupled to the processor; ports where each of the ports includes a respective power supply line; a switch; a hub operatively coupled to the ports and to the chipset for data transfer via an in-band protocol; and a microcontroller operatively coupled to the chipset, to the switch and to the hub where the microcontroller includes circuitry that controls the switch to transfer data to one of the ports via an out-of-band protocol and where the microcontroller includes circuitry that controls supply of power to the power supply lines.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A Basic Input/Output System (BIOS) secure data management system includes a BIOS that is configured to perform a boot process. At least one memory system is configured to provide a System Management (SM) memory location that is only accessible by the BIOS. A trusted platform module (TPM) includes at least one register and is configured to store sealed first secure data. The TPM is configured to use at least one first value in the at least one register that depends on the boot process to unseal the sealed first secure data to provide unsealed first secure data, and provide that unsealed first secure data to the BIOS for storage in the SM memory location. The BIOS is configured to retrieve the unsealed first secure data from the SM memory location and use the unsealed first secure data to perform a security function.

Abstract: A zone power cap for a power management zone that defines a limit of power consumption for the power management zone is determined. The power management zone comprises a plurality of components, wherein the power management zone is associated with a controller. A set of one or more characteristics of a workload associated with the power management zone is determined. A component power cap for one or more of the plurality of components is set based, at least in part, on the set of one or more characteristics of the workload and the zone power cap.

Abstract: Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.

Abstract: A network device manages multiple computers and connects the computers to boot devices that store boot programs used by the computers to boot. The network device downloads to each computer a respective boot order that specifies an order in which the computer is to attempt to boot from boot devices specified in the boot order. The network device automatically determines network paths over which each computer is to access the boot devices in the boot order for that computer. The network device automatically determines an availability of each network path and an availability of each boot device. The network device also receives boot status from each computer while the computer attempts to boot from boot devices in the boot order for that computer. The network device automatically performs boot-related actions based on the determined network path and boot device availabilities, and the received boot status.

Abstract: Technologies are generally described to provide a leakage current variability based power management of a processor. According to some examples, instruction counters and aggregated power consumption of the processor may be used to process power measurements of the processor into linear equations. The linear equations may be processed to produce a set of leakage values for the processor. In an example scenario, computation data from a power controller and processor instruction counters (PICs) of a core of the processor may be used to determine the leakage current variability of the core. A table of linear combination samples may be generated from the computation data. A micro-architectural leakage map of the core may be generated from the linear combination samples within the table.

Abstract: Methods for thermal management of an integrated circuit are disclosed. In particular, a dual control loop, having a first control loop and a second control loop, is used to maintain the temperature of an integrated circuit at a first temperature and a second temperature, respectively. In order to prevent the integrated circuit from overheating during periods of rapid temperature increase, the second control loop may be configured to control temperature at the second temperature below the specification limit of the integrated circuit by reducing power to the integrated circuit. The second control loop samples and maintains temperature of the integrated circuit at time intervals relatively faster than that of the first control loop. However, the second control loop is configured to release control to the first control loop when the temperature of the integrated circuit is reduced. The first control loop may then control power to the integrated circuit.

Abstract: A system and method for efficient management of operating modes within an integrated circuit (IC) for optimal power and performance targets. A semiconductor chip includes processing units each of which operates with respective operating parameters. Temperature sensors are included to measure a temperature of the one or more processing units during operation. A power manager determines a calculated power value independent of thermal conditions and current draw. The power manager reads each of a first thermal design power (TDP) value for the processing units and a second TDP value for a platform housing the semiconductor chip. The power manager determines a ratio of the first TDP value to the second TDP value. Additionally, the power manager determines another ratio of the first TDP value to the calculated power value. Using the measured temperature, the ratios and the calculated power value, the power manager determines a manner to adjust the operating parameters.

Abstract: Energy consumption analytics of a cloud based service is provided. An application such as a power analytics application monitors power consumption data of a server of the cloud based service. The power consumption data of the server is captured in a data file, a data store, a temporary storage, etc. The power consumption data is analyzed to detect power consumption metrics for the server. The power consumption metrics are presented in a business intelligence data structure.

Abstract: A computing system is associated with power consumption based on Power over Ethernet (PoE). Power consumption is compared to a threshold, and a signal is asserted that power consumption is to be limited based on the comparison to the threshold.

Abstract: Methods and apparatus relating to Active State Power Management (ASPM) to reduce power consumption by PCI express components are described. In one embodiment, a special packet with embedded information triggers entry into a lower power consumption state. The embedded information may include flow control credit information outstanding between two agents and the target power consumption state. Other embodiments are also disclosed and claimed.

Abstract: A power excursion warning system includes a power system having a first slew rate. A powered component is coupled to the power system. The powered component voltage regulator has a second slew rate that is greater than the first slew rate. A powered component voltage regulator is coupled to the powered component and operable to convert a first voltage received from the power system to a second voltage that is supplied to the powered component. A power excursion warning device is coupled to the powered component voltage regulator and operable to receive a signal from the powered component voltage regulator that is associated with the second slew rate, determine that the signal indicates a power excursion that will result in the power system operating outside a predetermined range, and produce a warning signal indicative of the power excursion.

Abstract: An apparatus and method for saving power of a USB composite network device is provided. The method includes sending an idle request IRP to a composite driver at a bus driver of a network driver when the composite network device requests selective suspend, sending power state transition information to the composite driver and shifting a power state from a normal state to an intermediate sleep state at the bus driver, and shifting a power state from the normal state to the intermediate sleep state at the composite driver according to the power state transition information, wherein, when the composite network device is shifted to the selective suspend mode, the bus driver and the composite driver are in the intermediate sleep state and an NDIS miniport driver of the network driver is in the normal state.

Abstract: According to an embodiment, an information processing apparatus includes: a first control unit to control a first device; and a second control unit to control a second device. The first control unit includes a first request processing unit, a notification unit, and a first execution unit. The second request processing unit receives a second request including an instruction to start a process of the second device. The notification unit notifies the second control unit that the first control unit receives a first request. The second execution unit executes a second request received by the second request processing unit when the first device is in the active state, and executes the second request stored in the storage unit when the notification is received by the notification receiving unit.

Abstract: Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.

Abstract: Function resources/memory resources and an associated resource controller configured to assign a first portion of the function resources/memory resources to at least one processing element in response to an access request from the processing element. The resource controller changes a power mode of the first portion of the function resources/memory resources as a function of the first portion assignment, and leaves an unassigned portion of the function resources/memory resources in a power down mode in a self-governing nature. The resource controller enables the processing element to access the first portion of the function resources/memory resources in response to the access request received from the processing element. The function resources/memory resources, resource controllers and one or more processing elements may comprise a system on a chip (SoC).

Abstract: A method operates an onboard power supply system in a motor vehicle. The onboard power supply system has a master controller and a slave controller, in which the master controller communicates with the slave controller via a subsidiary bus system and a further onboard power supply system component via a main bus system. Present requests are received in the slave controller and in response to the present requests, performing one of: putting the slave controller into an operating mode and switching the master controller to a transmission mode, in which the master controller coordinates communication between the slave controller and the onboard power supply system component; or putting the slave controller into a sleep mode and switching the master controller to an undertaking mode, in which the master controller responds to queries from the onboard power supply system component to the slave controller.