Abstract: Some embodiments of the present application are directed towards an integrated circuit (IC). The integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate electrode, a first electrode, and a dielectric layer. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate electrode is disposed on the semiconductor barrier layer. The first electrode is disposed at one side of the gate electrode. The first electrode includes a body portion and a vertical extension portion. The body portion is electrically connected to the semiconductor barrier layer, and the bottom surface of the vertical extension portion is lower than the top surface of the semiconductor channel layer. The dielectric layer is disposed between the vertical extension portion and the semiconductor channel layer. The first electrode is a conformal layer covers the semiconductor barrier layer and the dielectric layer.

Abstract: A power semiconductor device includes a wide-bandgap semiconductor layer having an active region and a termination region that laterally surrounds the active region. The wide-bandgap semiconductor layer has a first recess that is recessed from the first main side in the termination region and surrounds the active region and a second recess that is recessed from the first main side in the active region and is filled with an insulating material. A depth of the second recess is the same as a depth of the first recess. A field plate on the first main side of the wide-bandgap semiconductor layer exposes a first portion of the wide-bandgap semiconductor layer in the termination region.

Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a body region of the first conductivity type, a source region of a second conductivity type, a drain region of the second conductivity type, a gate electrode, a drift region of the second conductivity type, an implanted oxide layer, and a semiconductor region of the first conductivity type. The semiconductor region is formed to extend in a direction along the top face of the semiconductor substrate. A first distance and a second distance are set so that an intensity of 0.35 MV/cm or less is observed in an electric field of a first region including the end portion of the drift region and in an electric field of a second region between the end of the semiconductor region and the drain region.

Abstract: A light-emitting device and a method of manufacturing the same are provided. The light-emitting device may include a first electrode, a second electrode, and an interlayer located between the first electrode and the second electrode. The interlayer may include an emission layer that includes a first material, a second material, and a third material. The first material may include an inorganic semiconductor compound, an inorganic insulator compound, or any combination thereof. The second material may include a lanthanide metal. The third material may include an organic compound. An apparatus including the light-emitting device is provided.

Abstract: A micro LED display device includes a display substrate. The display substrate has a first transfer area and a second transfer area adjacent to each other. Both the first transfer area and the second transfer area include a plurality of pixel areas. The pixel area of the first transfer area includes a first micro light-emitting element arranged in a straight line along a first direction. The pixel area of the second transfer area includes a second micro light-emitting element arranged in another straight line along the first direction. In the first direction, the first micro light-emitting element and the second micro light-emitting element are arranged in a staggered manner. A manufacturing method of a micro LED display device is also provided.

Abstract: A power semiconductor device has a semiconductor layer structure that includes a silicon carbide drift region having a first conductivity type, first and second wells in the silicon carbide drift region that are doped with dopants having a second conductivity type, and a JFET region between the first and second wells. The first and second wells each include a main well and a side well that is between the main well and the JFET region, and each side well includes a respective channel region. A doping concentration of the JFET region exceeds a doping concentration of the silicon carbide drift region, and a minimum width of an upper portion of the JFET region is greater than a minimum width of a lower portion of the JFET region.

Abstract: A light-emitting device includes: a plurality of first electrodes respectively disposed in a first subpixel, a second subpixel, and a third subpixel; a second electrode facing the plurality of first electrodes; a first emission layer disposed in the first subpixel to emit a first-color light; a second emission layer disposed in the second subpixel to emit a second-color light; a first layer disposed between the second electrode and each of the first emission layer and the second emission layer, and integrated with the first subpixel, the second subpixel, and the third subpixel; a hole transport region disposed between the plurality of first electrodes and each of the first layer, the first emission layer, and the second emission layer; a first auxiliary layer disposed between the hole transport region and the first emission layer; and a first intermediate layer disposed between the first auxiliary layer and the first emission layer.

Abstract: The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer.

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

Abstract: A method for forming a high electron mobility transistor (HEMT) includes forming a buffer layer on a transparent substrate. The method further includes forming a barrier layer on the buffer layer. A channel region is formed in the buffer layer adjacent to the interface between the buffer layer and the barrier layer. The method further includes forming a dielectric layer on the barrier layer. The method further includes forming source/drain electrodes through the dielectric layer and the barrier layer and disposed on the buffer layer. The method further includes forming a shielding layer conformally covering the dielectric layer and the source/drain electrodes. The method further includes performing a thermal process on the source/drain electrodes.

Abstract: A solid-state imaging device including a first substrate having a pixel unit formed thereon and including a first semiconductor substrate and a first multi-layered wiring layer stacked, a second substrate having a circuit formed thereon and including a second semiconductor substrate and a second multi-layered wiring layer, the circuit having a predetermined function, and a third substrate having a circuit formed thereon and including a third semiconductor substrate and a third multi-layered wiring layer. The first substrate and the second substrate are bonded together such that that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other. The solid-state imaging device includes a first coupling structure and a second coupling structure. The first coupling structure electrically couples a circuit of the first substrate and the circuit of the second substrate.

Abstract: A light emitting device includes a substrate, a plurality of light emitting elements disposed in a light-emitting region on the substrate, at least one first wiring part surrounding the light-emitting region, at least one second wiring part, together with the at least one first wiring part, demarcating the light-emitting region into a plurality of demarcated regions, a first wall formed along and covering the at least one first wiring part to surround the light-emitting region, at least one second wall formed along and covering corresponding one or more of the at least one second wiring part, and a light-transmissive member containing a wavelength converting material, covering an entire light-emitting region.

Abstract: A power semiconductor including a gate, a source, a plurality of first long-strip source metal layer, a drain and a plurality of second long-strip drain metal layer is provided. The source includes a first copper particle layer and a first metal layer that covers the bottom surface of the first copper particle layer. The source is bonded to the first long-strip source metal layer via a first metal pillar. The drain includes a second copper particle layer and a second metal layer that covers the bottom surface of the second copper particle layer. The drain is bonded to the second long-strip drain metal layer via a second metal pillar. The thickness of the first copper particle layer and the second copper particle layer are 5 ?m˜100 ?m. The first copper particle layer and the second copper particle layer are formed by plating and stacking a plurality of large-grain copper.

Abstract: The present application discloses a method for fabricating semiconductor device with a graphene-based element. The method includes providing a substrate; forming a stacked gate structure over the substrate; forming first spacers on sidewalls of the gate stack structure, wherein the first spacers comprise graphene; forming sacrificial spacers on sidewall of the first spacers; and forming second spacers on sidewall of the sacrificial spacers.