Abstract: The present invention provides a method in a data processing system for efficiently sending a data packet from a source node to a destination node. The data processing system includes a multi-segment network having at least two segments, wherein the source node and the destination node are located within in different segments. Communication of a data packet from one segment to another segment is provided by an agent node. The present invention generates a data packet at the source node within a first segment on the multi-segment network. The data packet includes a source address, a destination address, and data. The data packet is then transmitted within the first segment and the source node retains ownership of the data packet. Thereafter, the data packet is received within the first segment at an agent node. The data packet is examined to determine the destination address and then transmit it to the destination node within a second segment in the multi-segment network.

Abstract: A communication network system in which a plurality of information processing equipments are connected with a communication line for communication of a message. The message contains an information data to be communicated among the information processing equipments. Each of the information processing equipments has its own programs and manual information items for each of the its own programs.

Abstract: Computer resources of a plurality of computers are managed by a resource manager of a master computer, and allotment of a server for a connection request is determined based on these physical and logical resources managed by the resource manager. A loosely coupled computer system can be regarded as one node when viewed from another system. When one computer in the loosely coupled computer system malfunctions, it is automatically replaced with another computer.

Abstract: A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.

Abstract: A peripheral interface unit (PIU) used by a microcontroller or microprocessor core having a pipelined architecture to access peripheral modules across a peripheral bus (PBUS). Data read or write accesses to registers in the core space are decoded and passed to the PIU. Then the access is executed across a peripheral address bus portion of the PBUS and a peripheral data bus of the PBUS by the PIU. In a pipelined architecture, during any one cycle there could exist up to two read accesses and one write access to the core registers. The PIU provides the needed logic to arbitrate these three access across the PBUS. In such cases the PIU inserts proper pipeline stalls until all the accesses are completed. All read accesses from the core registers cause at least a one state pipeline stall. Write accesses only stall the pipeline if two core register writes follow each other and the PBUS is not ready at the time of the second access or if a read and write occur at the same time.

Abstract: Output control circuit for a programmable logic controller, comprising a control unit (13) and a circuit (14) for controlling and checking output channels (11), including a deserializing section (16). The output circuit receives descending frames (T1) and ascending frames (T2) and, according to its configuration, it returns ascending frames (T3) to the control unit produced from frames (T1) and/or (T2).

Abstract: An internetwork device which manages the flow of packets of I/O data among a plurality of network interface devices includes a bus coupled to the plurality of network interface devices, a core memory storing only packets of I/O data and control structures needed by the plurality of network interface devices, and a processor including local memory isolated from the core memory storing routines and internetwork information involved in updating control structures and control fields in the packets of I/O data to direct movements of packets of I/O data among the plurality of network interface devices. A bus-memory interface is provided through which transfers of packets of I/O/data and control structures used by the plurality of network interface devices are conducted between the core memory and the bus. A processor-memory interface is provided through which transfers of data to or from control structures or control fields in packets of I/O data are conducted between the core memory and the processor.

Abstract: A processing element (42) design is provided for improving performance and reducing the number (30') of memory ports by eliminating the dedication of ports to specific functional units (22, 24, 26, 28) and by providing data paths (46, 48, 50, 52) to other forward results from functional unit outputs directly to other functional unit inputs.

Abstract: A data communicating apparatus adapted to be used in a small-sized personal instrument on a receiving side and arranged that data groups of a plurality of applications in a small-sized personal instrument on a transmitting side is used in the small-sized personal instrument on the receiving side, includes a unit for storing a plurality of data correlated each other in a state of keeping a correlation of each data according to a predetermined method, a unit connected to the storing unit for outputting the plurality of data stored in the storing unit, and a unit connected to both the storing unit and the outputting unit for controlling both the storing unit and the outputting unit in such a manner that the plurality of data are output from the storing unit with the state of keeping the correlation.

Abstract: To support increased speed of the FIFO, a flag logic circuit is incorporated within the FIFO which asserts the full flag and the empty flag with minimal delay. The flag logic circuit is faster since delays due to comparison logic are eliminated by generating an internal full or empty signal before the FIFO actually becomes full or empty.

Abstract: A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.

Abstract: A method for controlling a multi-tasking time slice to support a desired system frame operating time. Depending upon the number of tasks which take control within the desired system frame, and the length of the processing time required for each task, the system frame would extend beyond the desired system frame operating time. In this event, it is necessary to shorten the time slice so that subsequent frames remain as close as possible to the desired system frame operating time. Similarly, if extra time is left in each frame, then the slice time is expanded to allow tasks to complete processing within the desired system frame operating time without being sliced as often.

Abstract: Device drivers for removable system resources are configured dynamically in a computer system having a processor, a system memory and an interface for receiving removable system resources (generally denoted feature cards). A feature card has a card memory area which stores a device driver for controlling the feature card. The feature card device driver is separated into two parts: 1) a full device driver portion, and 2) a stub device driver portion. The full device driver provides all of the device driver functionality necessary to control each and every function of the feature card. The device driver stub is a small compact portion of processing logic for linking the full device driver with operating system software located in the computer system. A fixed amount of system memory RAM is set aside at bootstrap initialization to contain the device driver stubs.

Abstract: Device drivers for removable system resources are configured dynamically in a computer system which has a processor, a system memory and an interface for receiving removable system resources (generally denoted feature cards). A feature card includes a card memory area that stores a device driver for controlling the feature card. The feature card device driver is separated into two parts: 1) a full device driver portion, and 2) a stub device driver portion. The full device driver provides all of the device driver functionality necessary to control each and every function of the feature card. The device driver stub is a small compact portion of processing logic for linking the full device driver with operating system software located in the computer system. There is an upper bound for the size of a device driver stub of a given feature card. Any system will have a known number of card slots.

Abstract: A method for selecting the most cost-efficient configuration for backbone links in a distributed data network is disclosed. The method identifies candidate links between pairs of backbone nodes, evaluates the effect on the network of adding each candidate link to the network, and adds to the network those candidate links which produce a cost savings in the network. The method also routes data through the backbone to minimize transmission delays, and eliminates redundant lines from underutilized links, and removes from the network those links whose removal reduces the cost of the backbone.

Abstract: In circuitry which transfers data in streams in which a plurality of individual discrete groups of data are all addressed to the same address, apparatus for manipulating the data appearing in streams including a manipulation engine responsive to some portion of each group of the data transferred to cause the data to be manipulated in a particular manner.

Abstract: A method and apparatus for efficiently distinguishing between different types of input signals simulated by a pointing device coupled to a multi-tasking computer system. The pointing device may be a stylus, finger or other device that moves across the surface of a touch screen or the like to generate positional information. Depending on the response of a delay timer, the motion of the pointing device is recognized by software application programs as input information either from a mouse or from a gesture or a handwriting input mode. If motion cessation across the screen is detected with a predetermined time-delay period, the system accepts the input information in a mouse-emulating mode. If motion is detected within the predetermined time-delay period, the timer is reset. Thus, the system overhead associated with managing the timer can be reduced because the timer is periodically reset and need not be reset after each movement of the pointing device as in the prior art.

Abstract: A pipelined data server having an improved data transfer architecture is used with a distributed computer network and a plurality of secondary storage devices to efficiently transfer data between the network and the secondary storage devices. The pipelined, multiprocessor data server includes a common inter-processor bus that connects one or more communication processors and file processors to one or more device processors, each having a buffer memory as part of the device processor. The common bus provides for global direct access to each of the buffer memories in the device processors by any of the other processors. The buffer memories are also connected to the secondary storage device attached to the device processor by a DMA transfer path in the device processor. In this way, data transfers can occur between the secondary storage device and the network with only one data transfer across the common bus.

Abstract: A modular system for interfacing between a Navy standard UYK-43 computer a plurality of workstation consoles connected to a control data bus is provided. A first conversion processor is functionally connected to the computer and functionally connected to a backplane. A second conversion processor is functionally connected to the computer and functionally connected to the backplane. The second conversion processor also includes memory for storing status and action information associated with each of the consoles.

Abstract: A host interface comprising a reassembler for reassembling and decrypting data that has been encrypted in accordance with a pre-defined key and segmented into a plurality of asynchronous transfer mode (ATM) cells. Each cell comprises a virtual channel identifier (VCI), a multiplexing identifier (MID) if the data is transmitted using the CCITT specified Class 4 connectionless transfer ATM adaptation layer (AAL), and a cell body.