Abstract: A method of testing synchronous dynamic random access memories (SDRAMs) having a pair of memory banks, comprised of writing data into a first of the pair of memory banks at a first clock speed that can be used by a tester, transferring the data at a second clock speed much higher than the first clock speed from the first of the pair of memory banks to a second of the pair of memory banks, and then reading the second of the pair of memory banks at the first clock speed to the tester.

Abstract: In a speech decoding apparatus (100) supplied with an input speech signal (101) comprising successive blocks, each comprising a digital speech signal and an error detecting code signal, an error detector (8) detects an error in the digital speech signal by the error detecting code signal for each block to produce error detection pulses whenever the error detector detects the error. The error detector also produces the digital speech signals of the blocks. A speech decoder (9) decodes the digital speech signals of the blocks into an analog speech signal. A measuring circuit (102) measures, as a measured value, the number of the error detection pulses during a predetermined time interval. A comparator (15) compares the measured value with a reference value to produce a command signal when the measured value is greater than the reference value. A generator (12) generates an alarm signal in response to the command signal.

Abstract: A high performance transport layer checksum calculation unit and method is described for use in computer data communications systems which provides simultaneous general purpose data movement and checksum calculations. Data must be copied from the main memory of a computer in order to be transmitted and often a checksum must be calculated on the data for error detection purposes. The invention involves performing both of these tasks simultaneously thus requiring only one scan of the data memory. The checksum calculation method improves throughput capacity via a unique hardware architecture supporting delayed checksumming of packet segments. A net improvement for packets larger than a certain size is achieved via partial addition during DMA controlled memory access allowing improved average cycle time per data packet segment.

Abstract: A CRC operating unit which performs a CRC operation on received data using as an initial value a CRC operation result actual value obtained in a previous operation, and outputs a CRC operation result actual value. A delay unit delays the CRC operation result actual value by the time taken for a header part to be entered. The CRC operation result derivation unit outputs as a CRC operation result derivation value an operation result obtained by a CRC operation performed for all the receiving data of a header part provided with the above described CRC code using the CRC operation result actual value as an initial value. The coincidence detecting unit compares the CRC operation result actual value with the CRC operation result derivation value to detect the input timing of a header part as coincident timing for both values.

Abstract: An image processing system including a reconfiguration circuit, typically responding to fault detection. The image processing includes a data compressing unit for compressing image data generated by an image input terminal, a data storage unit for storing output compressed image data, a data decompressing unit for decompressing compressed data and for transferring the decompressed data to an output terminal. A control unit controls the system to compress and store image data, and then to repeatedly read out and transfer the stored data to the image output terminal. When a self diagnosis detects a fault in any one of the compressing unit, data storage unit, or data decompressing unit, the faulty unit is bypassed with a special data bus, thereby allowing system operating to continue.

Abstract: The system of the present invention has a plurality of sensors 1a, 1b and 1c and a system control circuit which includes a case memory portion and a work script memory portion. In response to application of state data from the sensors 1a, 1b and 1c, the system converts the state data into symbolic data. Then the symbolic data is evaluated to judge whether or not a fault exists and to specify a fault symptom. As a result of the judgement, a fault symptom and a fault in the objective machine are determined. Thereafter, cases stored in the case memory portion are retrieved on the basis of the results of the fault diagnosis and a fault simulation. A case which closely resembles the present state of the objective machine is selected. Then, repair work described in the selected case is executed.