Abstract: A voltage switching circuit is disclosed which is constructed from a minimum number of transistors and prevents the threshold voltage margin from being lowered by causing high-voltage cutoff and supply voltage transfer functions heretofore performed by a single depletion transistor to be shared between two series-connected depletion transistors different in gate insulating film thickness or threshold voltage. Thus, without using enhancement transistors which involve an increase in pattern area a voltage switching circuit can be provided which is small in chip area, low in cost and high in yield and reliability and provides a stable operation with a low supply voltage which is impossible with one depletion transistor.

Abstract: A fuse circuit comprises a plurality of enable fuse units and a plurality of fuse sets. Current flows at a reset mode in the plurality of enable fuse units, and the flowing of current is controlled by enable signals outputted from the plurality of enable fuse units in the plurality of fuse sets. In the fuse circuit, a fuse set connected to the end of the enable fuse unit whose fuse is disconnected selectively performs a reset operation, thereby reducing peak current to decrease the whole current consumption.

Abstract: A CMOS analog switch is provided that can handle negative input polarity. The semiconductor substrate wherein the analog switch is formed has a substrate area of n-conductivity type. First and second p-channel transistors are formed in the n-conductivity substrate area and each have a gate, a source connected to the input terminal and a drain connected to the output terminal. The analog switch further has a comparator for comparing a voltage level at the input terminal with ground level, a switch driven by an output of the comparator to selectively connect the n-conductivity area with the signal input terminal for a positive input voltage level or to ground for a negative input voltage level, and control circuitry providing gate control signals for the first and second p-channel transistors. The inherent substrate diodes are effectively kept from becoming conductive.

Abstract: In a load driving circuit, a detection current Is (=Io/N), 1/N of a driving current Io, flows in a detection resistor, where N indicates a shunt ratio between a current (=driving current Io) that flows in an output source (S1) and a current (=detection current Is) that flows in a detection source (S2). The shunt ratio is determined by a cell ratio between the output source (S1) and the detection source (S2).

Abstract: In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were transmitted over the line. If the bit on the line has been static for several clock cycles, the slew rate will be increased to facilitate correct reading of the bit for the next clock cycle. If the bit on the line has been dynamic for the previous bits, the slew rate will be a lower slew rate to avoid crosstalk between neighboring lines.

Abstract: The present invention relates to a high efficiency three-level inverter apparatus containing both bipolar and field effect transistors. An embodiment of a modified control scheme is also presented whereby transistors are modulated differently for each quadrant of output voltage-current phase. This embodiment of a modified control scheme allows efficient switching of field effect transistors without additional freewheeling and series diodes.

Abstract: A power-up circuit of a semiconductor memory device includes a power supply voltage level follower unit for providing a bias voltage which is linearly varied according to variation of a power supply voltage, a power supply voltage detection unit for detecting the variation of the power supply voltage to a predetermined critical voltage level in response to the bias voltage, and a reset prevention unit for canceling variation of the detection signal due to a power drop by delaying level transition of the detection signal according to decrease of the power supply voltage.

Abstract: A drive circuit applies a drive voltage through an outputs terminal to a switching element. The drive circuit includes a supplying circuit, an amplifying circuit, a detecting circuit, and an adjusting circuit. In response to a control signal, the supplying circuit generates a first drive current. The amplifying circuit generates and applies a second drive current, which is larger than the first drive current, to the output terminal for changing the drive voltage. The detecting circuit is coupled to the output terminal for generating a detection signal representative of the drive voltage. Based on the detection signal, the adjusting circuit implemented by a differential comparator dynamically adjusts the first drive current.

Abstract: A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector generates a second output signal if the feedback clock signal lags the reference clock signal by more than a second time. If the feedback clock signal either leads the reference clock signal by less than the first time or lags the reference clock signal by less than the second time, neither output signal is generated. The phase detector may be used in a delay-lock loop in which the first and second output signals increase or decrease a delay of the reference clock signal by respective first and second delay increments. In such case, the each of the first and second delay increments should be less than the sum of the first and second times.

Abstract: The invention recognizes that sampler linearity is degraded because transfer voltage across a sampler's buffer varies with amplitude of the analog signal being sampled. Because this transfer voltage is in the signal path it modulates the signal and distorts the resulting sample. In the invention, sampler embodiments are provided which include replica current generators that provide and route sample currents to sample capacitors so that an associated buffer transistor can transfer a faithful copy of the analog signal's potential to the sample capacitor and thereby significantly enhance the sampler's linearity. The replica current generators generally include a replica load that mimics the sample load driven by the buffer transistor.

Abstract: A sample and hold circuit including a plurality of input signal sampling switches using native NMOS transistors in combination with switched bulk PMOS transistors. The input signal sampling switches input a differential input signal and output an intermediate differential signal. A plurality of capacitors are connected to the intermediate differential signal. A plurality of summing junction switches receive charge stored on the plurality of capacitors, and output a differential sampled and held charge to the summing junction. The plurality of input signal sampling switches include first, second, third, and fourth switches each having an input and an output. Inputs of the first and third switches are connected to a first voltage of the differential input voltage. Inputs of the second and fourth switches are connected to a second voltage of the differential input voltage. Outputs of the first and second switches are connected together and to an input of a first capacitor of the plurality of capacitors.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: An apparatus for controlling operation of a processor device during startup of the processor device includes: (a) a signal treating circuit receiving a voltage supply signal at a voltage supply locus; the signal treating circuit using the voltage supply signal for generating a first treated signal and a second treated signal; and (b) an output circuit coupled with the signal treating circuit; the output circuit receiving the first treated signal and the second treated signal and generating a control signal at an output locus based upon a relationship between the first treated signal and the second treated signal; the output locus being coupled with the processor device; the control signal effecting the controlling.

Abstract: A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor.

Abstract: A reference voltage and an input signal voltage are applied to gates of FETs each equipped with a LOCOS-drain structure, respectively, and currents according to the voltages are made to flow from a power supply voltage Vbat to drain sides through resistors and sources, respectively. The currents are made to flow in FETs to be converted to voltages. Then, both voltages are compared in a comparator. When a potential of a reference voltage input terminal in the comparator that operates with power provided by a power supply Vcc tends to rise above a predetermined level, a FET is turned on and clamps the voltage so as to suppress its potential rise.

Abstract: Control circuit for an IGB transistor, which comprises means (T1, V1, C3, C4) for generating auxiliary voltage, a first and a second controllable control switches (V8) connected in series between the auxiliary voltage, and a gate resistor (Rg). The control circuit further comprises a boost capacitor (Cg) connected in series with the gate resistor (Rg), a resistor (R3) whose first terminal is connected to the second terminal (4) of the boost capacitor and whose second terminal is connected to the intermediate voltage level of the auxiliary voltage of the control switches, a Zener diode (V9) whose anode is connected to the point between the gate resistor and the boost capacitor and whose cathode is connected to the point between the boost capacitor and the resistor (R3), and a diode (V10) whose anode is connected to the cathode of the Zener diode (V9) and whose cathode is connected to the positive terminal of the auxiliary voltage of the control switches.

Abstract: Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback clocks to a reference clock to generate phase measurement values. A common delay is removed from the phase measurement values to form normalized correction values. Target phase values and clock select values are selected using the normalized correction values. And, clock signals to independent ASIC modules are adjusted based on the target phase values and clock select values.

Abstract: To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter that converts the close-loop's voltage to a current and supplies a first voltage to the first and second transistors. The third and fourth currents are scaled replicas of a different current flowing through a current mirror of the voltage-to-current converter and that supplies a second voltage to the third and fourth transistors.

Abstract: A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further determine whether the falling edge of the output clock should be triggered by the rising or the falling edge of the falling edge of the input clock signal. The counter may be implemented as a M/N:D counter in which a phase accumulator is compared to predetermined values to select the rising and falling edges of the output clock signal. In a default condition, the rising and falling edges of the output clock signal are triggered by rising edges of the input clock signal. However, if the accumulated phase value is greater than or equal to M/2 and less than M, an overriding signal will trigger the rising edge of the output clock based on the falling edge of the previous input clock cycle.

Abstract: An output driver. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for controlling the magnitude of the variable current in accordance with the input signal. In an illustrative embodiment, the third circuit is adapted to generate a controlling current in accordance with the input signal, and the second circuit includes a current mirror adapted to receive the controlling current and output a scaled version of the controlling current to the output node.