Abstract: The present invention concerns a circuit and method to automatically test and disable defective rows in a FIFO or other buffer where the wordlines or rows of the FIFO buffer are driven by a shift register scheme. Additional enabled rows may be placed within the normal memory array. The additional enabled rows are substituted, as needed, for one or more defective rows. As a result, a defective row can be automatically disabled without effecting the operation of the FIFO, particularly the read or write data path. In one example, the disabling effect is achieved by using a comparison circuit to determine if the words read from the memory are accurate. The present invention can be used to effectively bypass any single shift register element or a multiple number of shift register elements.

Abstract: In a semiconductor device, a plurality of functional test patterns are generated and transmitted to the semiconductor device, and it is determined whether or not an abnormal current, flows through the semiconductor device. Also, the semiconductor device is irradiated with electrons, and secondary electrons from the semiconductor device are detected. Potential contrast images are calculated in accordance with the detected secondary electrons in response to the functional test patterns. A logic operation is performed upon the potential contrast images to estimate a fault point.

Abstract: A high performance register that can be used as a pipelined register in logic chips that are designed using a pulsed logic methodology is described. The register features minimal setup time, pulse catching and pulse launching. The register circuitry complies with and implements a circuit-level test methodology for pulsed logic that features the ability to inhibit the reset of pulses, to force resets and to operate the circuits in a pseudo static mode. The register also complies with the level sensitive scan design (LSSD) methodology. Also described is a state-holding static master-slave register that complies with a pulsed logic design methodology, the register exhibiting an automatic power reduction feature and a simplified modular register bit design which can easily be adapted to either static domino or pulsed logic. The register is also LSSD compliant. Also described is the means and method for allowing static transmission gate input registers to comply with the static evaluate test mode.

Abstract: A data storage system is provided having a faster data transfer rate and reduced complexity though improved control of timing. The data storage system has a plurality of storage devices and a plurality of data buses through which data are transferred. An input/output unit interleaves a plurality of data between an interface and the plurality of data buses while transferring data. A first and a second latch unit, serially connected between the storage devices and the data bus, retain data.

Abstract: Circuits and methods of testing an integrated circuit die are disclosed. Active logic setting circuits are incorporated into input cells of a die. During testing, the active logic setting circuits weakly drive the input cells to a definite logic level. Therefore, the necessity of connecting probes to all of the input pads to prevent floating signals in the die is eliminated. Furthermore, during normal operations the active logic setting circuits have little or no effect on the performance of the die.

Abstract: In a semiconductor device formed by a plurality of logic blocks, plurality of functional test patterns are generated and transmitted to the semiconductor device. If an abnormal current is detected upon receipt of an i-th functional test pattern, and an output data is different from an expected data upon receipt of a j-th functional test pattern, a fault block is determined in accordance with the i-th functional test pattern and the j-th functional test pattern.

Abstract: A system and method for extracting custom debug signals from an integrated circuit chip. The custom debug signals, which are normally extracted via bonded custom debug pads during the testing of the chip, are made available in production chips, where the custom debug pads are not bonded and therefore unavailable, via the external I/O bus of the integrated circuit. In a preferred embodiment, the integrated circuit operates normally to drive standard debug data from internal nodes of the integrated circuit onto the I/O bus during idles cycles in the normal operation of the integrated circuit. Selection means may be set to drive the custom debug signals onto the I/O bus during idle cycles of normal integrated circuit operation rather than the standard debug data.