Abstract: An array of deep trenches is formed in a doped portion of the semiconductor substrate, which forms a lower electrode. A dielectric layer is formed on the sidewalls of the array of deep trenches. The array of deep trenches is filled with a doped semiconductor material to form an upper electrode comprising a top plate portion and a plurality of extension portions into the array of trenches. In a depletion mode, the bias condition across the dielectric layer depletes majority carriers within the top electrode, thus providing a low capacitance. In an accumulation mode, the bias condition attracts majority carriers toward the dielectric layer, providing a high capacitance. Thus, the trench metal-oxide-semiconductor (MOS) varactor provides a variable capacitance depending on the polarity of the bias.

Abstract: A carrier storage layer is located in a region of a predetermined depth from a surface of an N? substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N? substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N? substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.

Abstract: A multi-LED package includes a heat sink including a primary slug and a secondary slug separated from each other, a primary LED chip mounted on the primary slug, one or more secondary LED chips mounted on the secondary slug, a lead frame structure electrically wired to the primary and secondary LED chips, and a phosphor covering at least a part of the primary LED chip. Another multi-LED package includes a heat sink having an upper surface and partitions protruding therefrom, a primary LED chip mounted inside the partitions, one or more secondary LED chips mounted outside the partitions, a lead frame structure electrically wired to the primary and secondary LED chips, and a phosphor covering at least a part of the primary LED chip.

Abstract: Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.

Abstract: The present invention provides an array substrate and a method for manufacturing the same. The array substrate comprises a substrate and a plurality of gate lines parallel to each other and a plurality of data lines parallel to each other formed on the substrate, the gate lines intersecting the data lines to define a plurality of pixel region arranged in a matrix, each pixel region comprising a thin film transistor, a pixel electrode and a thin film diode. With respect to each pixel region in a row, the pixel electrode is connected with the gate line in the present row through the thin film transistor and is connected with the gate line in a previous row through the thin film diode.

Abstract: A microlens array is provided, including a base layer with a plurality of first microlenses formed over a first region thereof, wherein the first microlenses are formed with a first height. A plurality of second microlenses are formed over a second region of the base layer, wherein the second region surrounds the first region and the second microlenses are formed with a second height lower than the first height. A plurality of third microlenses are formed over a third region of the base layer, wherein the third region surrounds the second and three regions, and the microlenses are formed with a third height lower than the first and second heights.

Abstract: A semiconductor photosensitive element comprises: a semiconductor substrate of a first conductivity type; a first light absorption layer, a first semiconductor layer of a second conductivity type, a first semiconductor layer of the first conductivity type, a second light absorption layer, and a second semiconductor layer of a second conductivity type, arranged in this order on the semiconductor substrate; a first electrode connected the second semiconductor layer of the second conductivity type; a second electrode connected to the semiconductor substrate; and a third electrode electrically connecting the first semiconductor layer of the first conductivity type to the first semiconductor layer of the second conductivity type. The third electrode is located outside a light detection region for detecting optical signals.

Abstract: An organic thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode. A gate insulating layer is formed on the gate electrode and a data line is formed on the gate insulating layer, intersecting the gate line, and including a drain electrode. A source electrode is formed on the gate insulating layer and is spaced apart from the drain electrode, enclosed by the drain electrode. A bank insulating layer includes a first opening exposing the drain electrode and the source electrode and a second opening which exposes at least a portion of the source electrode. An organic semiconductor is formed in the first opening and contacts the drain electrode and the source electrode. A pixel electrode contacts the source electrode through the second opening.

Abstract: A solid-state imaging device includes: an imaging area in which light receiving portions are disposed; an interconnect layer disposed on the light receiving portions, the interconnect layer including metal interconnects having openings and first insulating films; inner-layer lenses formed over the interconnect layer in one-to-one relationship with the light receiving portions; a transparent second insulating film formed on the interconnect layer and the inner-layer lenses; top lenses formed on the second insulating film in one-to-one relationship with the light receiving portions, an upper face of each of the top lenses being a convexly curved face; and a transparent film on the top lenses, the transparent film being formed of a material having a refractive index smaller than a refractive index of the top lenses. In this way, a focal point of at least part of incident light can be situated above a semiconductor substrate.

Abstract: A non-volatile memory device which can be highly-integrated without a decrease in reliability, and a method of fabricating the same, are provided. In the non-volatile memory device, a first doped layer of a first conductivity type is disposed on a substrate. A semiconductor pillar of a second conductivity type opposite to the first conductivity type extends upward from the first doped layer. A first control gate electrode substantially surrounds a first sidewall of the semiconductor pillar. A second control gate electrode substantially surrounds a second sidewall of the semiconductor pillar and is separated from the first control gate electrode. A second doped layer of the first conductivity type is disposed on the semiconductor pillar.

Abstract: In a semiconductor device including a bipolar transistor, a base region has a two layer structure including a first base region, and a second base region which is provided around the first base region and has a lower impurity density than that of the first base region and has a shallower depth than that of the first base region.

Abstract: This invention provides a circuit bonding detection device, a detection method thereof and an electro-optical apparatus incorporating the circuit bonding detection device. The circuit bonding detection device includes a substrate, a circuit module, a set of sensors, and a detection unit. A plurality of contact pads is disposed on the substrate. The circuit module includes a plurality of conductive bumps corresponding to the contact pads. The sensors are disposed on two sides of at least one of contact pads or of the corresponding conductive bumps. The detection unit is electrically coupled with the set of sensors and transmits a fault signal when at least one of the contact pads and the corresponding conductive bumps deforms and contacts the sensors.