Patents Examined by Nanci N Wong
  • Patent number: 11656765
    Abstract: A data bus inversion (DBI) circuit of a memory device includes a first processing component configured to generate first combination data by combining read data read from a memory cell region and previous data previously outputted from a data line, and generate second combination data by selectively inverting the first combination data depending on a result of comparing the first combination data and the previous data; and a second processing component configured to generate data to be outputted from the data line, by combining the second combination data and the previous data, wherein the second processing component generates bits of unnecessary bit positions in the data to be the same as bits of the unnecessary bit positions in the previous data.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 23, 2023
    Assignee: SK hynix Inc.
    Inventors: Yong Sang Park, Dae Woo Kim, Min Soo Lim, Young Duke Seo
  • Patent number: 11656794
    Abstract: Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A tinier of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Nadav Grosz, David Aaron Palmer
  • Patent number: 11644978
    Abstract: A system shares I/O load between controllers in a high availability system. For writes, a controller determines based on one or more factors which controller will flush batches of data from write-back cache to better distribute the I/O burden. The determination occurs after the local storage controller caches the data, mirrors it, and confirms write complete to the host. Once it is determined which storage controller will flush the cache, the flush occurs and the corresponding metadata at a second layer of indirection is updated by that determined storage controller (whether or not it is identified as the owner of the corresponding volume to the host, while the volume owner updates metadata at a first layer of indirection). For a host read, the controller that owns the volume accesses the metadata from whichever controller(s) flushed the data previously and reads the data, regardless of which controller had performed the flush.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: May 9, 2023
    Assignee: NETAPP, INC.
    Inventors: Randolph Sterns, Charles Binford, Joseph Blount, Joseph Moore, William P. Delaney
  • Patent number: 11630769
    Abstract: A memory controller includes a buffer memory and a microprocessor. The buffer memory includes at least a first cache memory and a second cache memory. The microprocessor is configured to control access of a flash memory device. The microprocessor is configured to obtain a number of spare blocks of the flash memory device corresponding to a first operation period, determine a write speed compensation value, determine a target write speed according to the write speed compensation value and a balance speed, and determine a target garbage collection speed according to the target write speed. The microprocessor is further configured to perform one or more write operations in response to one or more write commands received from a host device in the first operation period according to the target write speed and perform at least one garbage collection operation according to the target garbage collection speed.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: April 18, 2023
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Yao Chiang
  • Patent number: 11620068
    Abstract: Techniques for performing data transfers may include determining a first page of user data to be transferred from a source data storage system to a target data storage system, wherein the source data storage system has a source page size granularity denoting a first size of backend I/O operations on the source data storage system, wherein the target data storage system has a target page size granularity denoting a second size of backend I/O operations on the target data storage system; performing processing on the source data storage system that constructs a second page of user data that is the second size, wherein the second page of user data includes the first page of user data that is the first size and another page of user data that is the first size; and transferring the second page of user data from the source to the target data storage system.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: April 4, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Amitai Alkalay, Lior Kamran, Vasu Subramanian
  • Patent number: 11620069
    Abstract: Example implementation described herein are directed to a mechanism to provision data volume which requires remote data copy between separated clusters, especially for the container platform. For a request to create a volume made to the clusters, example implementations can involve creating a first volume in a first cluster; obtaining volume information of a corresponding second volume from a second cluster; configuring the first volume and the corresponding second volume in the second cluster to have a remote copy relationship based on the obtained volume information; and setting access from the container to the first volume and the corresponding second volume based on the remote copy relationship.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: April 4, 2023
    Assignee: HITACHI, LTD.
    Inventors: Akiyoshi Tsuchiya, Tomohiro Kawaguchi
  • Patent number: 11609695
    Abstract: A data model is trained to determine whether data is raw, compressed, and/or encrypted. The data model may also be trained to recognize which compression algorithm was used to compress data and predict compression ratios for the data using different compression algorithms. A storage system uses the data model to independently identify raw data. The raw data is grouped based on similarity of statistical features and group members are compressed with the same compression algorithm and may be encrypted after compression with the same encryption algorithm. The data model may also be used to identify sub-optimally compressed data, which may be uncompressed and grouped for compression using a different compression algorithm.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: March 21, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: John Krasner, Sweetesh Singh
  • Patent number: 11604589
    Abstract: A throttling value is determined according to one of multiple throttling modes. A threshold value is determined. The throttling value is compared to the threshold value. A request mask is generated based on a result of the comparison of the throttling value to the threshold value. In response to detecting the request mask, an arbitration request is masked using the request mask prior to passing the arbitration request to an arbitration component that manages access of multiple client requestors to a buffer. The arbitration request is generated in response to receiving an access request for the buffer from a client requestor of the multiple client requestors.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Michael Ou
  • Patent number: 11599291
    Abstract: Restoring data stored by a backup process in an object store of a cloud network by initiating a restore request to a server accessing the object store, by providing a source identifier of one or more data blocks of the requested data and a timestamp for a backup image at a requested point in time (PIT). The server manages a queue of blocks in temporary storage to provide blocks for retrieval by the client, and initially fills the queue with blocks from a full backup and unchanged by any incremental backup to the requested PIT. In response to the request, the server assembles blocks that are changed from the full backup through one or more incremental backups to the requested PIT using a full block synthesis process employing forward and reverse delta objects, and sends to the client the blocks initially filled in the queue with the assembled blocks to return a full PIT backup image for the requested PIT.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: March 7, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Mark Malamut, Arun Murti, Adam Brenner, Lev Ayzenberg, Sharon Vitek, Jehuda Shemer
  • Patent number: 11599465
    Abstract: An incoming write request received from a client is accessed. The incoming write request comprises a write command to transfer write data to a buffer memory. An initial portion of the write data is written to the buffer memory. An alignment of a final portion of the write data with respect to a memory bank width of the buffer memory is determined. The client is determined to be designated as a burst-overwrite client. In response to determining that the final portion of the write data is unaligned with the memory bank width of the buffer memory, the final portion of the write data is written to the buffer memory without preserving previously stored data based on the client being designated as a burst-overwrite client.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Michael Ou
  • Patent number: 11599288
    Abstract: In one aspect, a computerized method includes the step of building an information technology operations analytics (ITOA) stack. The method includes the step of ingesting and storing data at rest. The method includes the step of storing a set of metadata of the ingested data in a virtual machine or a container. The method includes the step of maintaining a set of primary data of the ingested data with an object store. The method includes the step of packaging one or more data units of the set of primary data. The method includes the step of writing over objects at select intervals. The method includes the step of breaking objects into chunks to reduce overwrites. The method includes the step of laying the data out as partitioned by time. The method includes the step of creating one or more application boundaries at the time of ingesting.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 7, 2023
    Inventor: Ranjan Parthasarathy
  • Patent number: 11556248
    Abstract: In some examples, a master die may receive data from one or more slave die. The master die may provide data from the master die and the data from the one or more slave die to a plurality of output terminals. Data from the master die may be provided for a portion of a data burst and data from the slave die may be provided for another portion of the data burst. In some examples, a master die may provide data to one or more slave die. The master die may provide data to the master die and the data to the one or more slave die from a plurality of input terminals. Data from the input terminals may be provided to the slave die for a portion of a data burst and data may be provided from the master die for another portion of the data burst.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: January 17, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Scott Eugene Smith
  • Patent number: 11550507
    Abstract: A timing detection circuit includes: a delay circuit in which a plurality of cascade connected delay elements are arranged in a matrix; a plurality of odd-numbered row column lines provided in each column for each set by dividing odd-numbered rows into a plurality of sets; a plurality of even-numbered row column lines provided in each column for each set by dividing even-numbered rows into a plurality of sets; a first logical operation circuit performs a logical operation on levels of the odd-numbered row column lines and outputs a first operation result to a second latch; a second logical operation circuit performs a logical operation on levels of the plurality of even-numbered row column lines and outputs a second operation result to a third latch; and a control circuit given the first operation result and controls charging of the odd-numbered and even-numbered row column lines based on the second clock.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: January 10, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Yohei Yasuda
  • Patent number: 11550710
    Abstract: A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: January 10, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wei-Ren Hsu, Chih-Yen Chen, Yen-Chung Chen, Jiunn-Jong Pan
  • Patent number: 11544181
    Abstract: A storage device includes a controller and nonvolatile memories. The controller receives write commands having virtual stream identifiers (IDs), receives discard commands having the virtual stream IDs, and determines a lifetime of write data to which each of the virtual stream IDs is assigned. The nonvolatile memories are accessed by the controller depending on physical stream IDs. The controller maps the virtual stream IDs and the physical stream IDs based on the lifetime of the write data.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: January 3, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwanjin Yong, Jin-Soo Kim
  • Patent number: 11537510
    Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a storage unit divided into a plurality of streams. The storage unit comprises a plurality of dies, where each die comprises two planes. One erase block from each plane of a die is selected for stream formation. Each erase block comprises a plurality of wordlines. A stream comprises one or two dies dedicated to storing parity data and a plurality of dies dedicated to storing user data. The stream further comprises space devoted for controller metadata. The storage device restricts a host device to send write commands in a minimum write size to increase programming efficiency. The minimum write size equals one wordline from one erase block from each plane of each die in the stream dedicated to storing user data minus the space dedicated to metadata.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Alan D. Bennett, Daniel L. Helmick, Liam Parker, Sergey Anatolievich Gorobets, Peter Grayson
  • Patent number: 11520487
    Abstract: Exemplary methods, apparatuses, and systems include a memory controller detecting that an asynchronous power loss event has occurred. Upon determining that a write operation is in progress to a first type of non-volatile memory element, the memory controller cancels the write operation and retrieves data associated with the write operation. The memory controller sends a request for a second physical address pointing to a second type of non-volatile memory element. Upon receiving a second physical address corresponding to a logical address, the memory controller stores the data at the second physical address.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 6, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael W. Sheperek, James P. Crowley
  • Patent number: 11520807
    Abstract: Technology for interoperability is disclosed by enabling the sharing of application state data for an application experience across computing devices, operating systems, applications, or locations. In one aspect, a secondary application shares encrypted state data along with a non-encrypted hint that describes the application experience reflected in the state data with a primary application. The primary application is then able to use the hint to determine that a user is interested in returning to the experience in the secondary application. The primary application then transfers the encrypted state data to the secondary application, which uses the state data to return the application to the application experience. A platform and an application programming interface (API) are provided for computer applications and services to store and retrieve application state data associated with an event.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: December 6, 2022
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Jonathan Rabin, Dikla Dotan-Cohen, Daniel Avigdor
  • Patent number: 11513715
    Abstract: A method that is performed for backing up data. The method includes obtaining, by a backup storage, an incremental backup request; and in response to the incremental backup request, identifying backup extents of a full backup associated with the incremental backup request using backup metadata; generating an intermediate backup file comprising the backup extents, wherein each of the backup extents is a reference to a correspond data block; obtaining modified data blocks from a production host; and updating the intermediate backup file using on the modified data blocks to generate a virtual synthetic backup file.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Ravi Kishore Yadav Rangapuram, Manjunath Jagannatha, Kiran Kumar Madiraju Varadaraju
  • Patent number: 11500563
    Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may, when setting a firmware as a target firmware, generate a plurality of test commands to test the target firmware, test the target firmware by processing the plurality of test commands, and randomly generate logical block address (LBA) values corresponding to each of the plurality of test commands based on a seed value corresponding to each of the plurality of test commands.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: November 15, 2022
    Assignee: SK hynix Inc.
    Inventor: In Jong Jang