Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.

Abstract: A leadframe (1) includes a main frame having longitudinal outer rails (4) and a number of sub-frame (8) separated from the main frame by a slit (6) extending around at least part of the perimeter of the sub-frame (8). A plurality of flag portions (2), on which a semiconductor die is to be mounted, extend from the mainframe and a plurality of lead portions (12) extend from the sub-frame (8) towards the flag portions (2). The sub-frame (8) is bent twice in a zig-zag fashion so as to be in a plane parallel to that of the main frame so that the corresponding flag and lead portions overlap without affecting the dimensions of the outer edge portion of the main frame.

Abstract: A semiconductor device card receiving a circuit substrate (1) which has electronic component parts (2) assembled therein, comprises a pair of metal sheets (10, 10) forming a front and a back surfaces of the card and a pair of opposed resin-made frames (11, 12) surrounding peripheries of the respective metal sheets to be connected by embedding bent portions 100 of the peripheries of the metal sheets (10, 10) into the resin-made frames (11, 12), and the paired opposed frames are provided at their contact end portions with fusible projections (13) and grooves (14) adapted to engage with the projections (13) and are connected to each other by fusing at least a leading end of the projection (13) within the groove (14).

Abstract: An LOC die assembly including a die dielectrically adhered to the underside of a lead frame. The adhesive is applied over a minimum cross-sectional area and number of attachment points to maximize flexure of leads extending over the active surface of the die. In this manner, flexure of the leads to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant is maximized, and the point stresses on the active surface caused by the filler particles are reduced by the lead flexure.

Abstract: A semiconductor device package and method includes a thick, integrated circuit chip stack having a substantially planar bottom surface with a plurality of terminals. A carrier substrate is provided, also having a substantially planar surface, and being adapted to mount the chip stack. The substrate has a plurality of terminals and may preferably be made of a metallized ceramic. The terminals of the chip stack are adapted to be connected to the terminals of the substrate. Means are provided for mounting the chip stack on the substrate, as well as means for making electrical connections between the terminals of the chip stack and the terminals of the substrate. Finally, encapsulating means are used for supporting and maintaining the chip stack mounted on the carrier substrate. J leads connect the substrate to a circuit card.

Abstract: A semiconductor device comprises two adjacent semiconductor layers of different materials forming a heterojunction therebetween. A first layer has a larger gap between the conduction band and the valence band that a second layer at the interface between the layers. The second layer is made of SiC and the first layer is made of one of at least a) AlN and b) an alloy of AlN and other Group 3B-nitride.

Abstract: An improved Silicon-On-Insulator (SOI) semiconductor device having a first and second asymmetric transistor, each having a source, a body, a gate, and a drain. The respective gates and drains of the asymmetric transistors are connected together such that a transistor pair is formed which is operable as a single symmetric transistor. An NMOS transistor pair may be connected in parallel with a PMOS transistor pair so as to form a symmetric Pass Gate.