Patents Examined by Nathan K. Kelly
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Patent number: 5942791Abstract: A method of fabricating a microbridge structure for a thermal detector array comprises growing a planarising layer on a substrate, growing a ferroelectric material layer on the planarising layer and then etching the planarising layer away, either wholly or partially, to leave a ferroelectric microbridge having a uniform thickness. The planarising layer may be a sacrificial layer or may comprise a sacrificial layer as well as other layers.Type: GrantFiled: March 4, 1997Date of Patent: August 24, 1999Assignee: GEC-Marconi LimitedInventors: Nicholas M Shorrocks, Martin J Walker, Ralph Nicklin, Andrew D Parsons
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Patent number: 5877549Abstract: An improved UFBGA package equipped with an interface assembly having external electrode protrusions, an anisotropic conductive film, and a photosoluble film, which includes an interface assembly provided at the lower portion of the substrate.Type: GrantFiled: January 2, 1996Date of Patent: March 2, 1999Assignee: LG Semicon Co., Ltd.Inventor: Jin Sung Kim
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Patent number: 5818108Abstract: The invention concerns an MCM type high-density assembly of integrated circuits having a high reliability by virtue of its design and the means employed in its implementation. The essential feature of the assembly is the presence of one or more interconnection substrates in addition to at least one substrate carrying a plurality of unencapsulated electronic chips connected to the interconnection substrate(s) by conventional microwiring techniques, preferably through one or more apertures in the substrates. The interconnection substrate(s) is or are advantageously of the multilayer type. The assembly is adapted to be encapsulated thereafter in a hermetically sealed case in the manner that is standard for MCM.Type: GrantFiled: April 14, 1997Date of Patent: October 6, 1998Assignee: Alcatel N.V.Inventors: Eric Muller, Marc Masgrangeas, Augustin Coello Vera
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Patent number: 5801406Abstract: A mask programmable integrated circuit having a plurality of iterative building blocks. Each building block has at least two adjacent basic base arrays. Each base array is comprised of an array of sites which, after personalization, form an array of logic blocks. Fabricated between the basic arrays is bridging circuitry. The generic layers of bridging circuitry are comprised of an array of sites. In order to fabricate the customized integrated circuit, personalization layers are fabricated over the generic layers. The personalization layers are arranged such that a particular integrated circuit design can utilize as many basic arrays as necessary to implement the desired logic functionality. After personalization, the bridging circuitry is comprised of logic blocks and interconnect.Type: GrantFiled: June 28, 1995Date of Patent: September 1, 1998Assignee: Asic Technical SolutionsInventors: Ray N. Lubow, Kashmira Singh Johal
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Patent number: 5793061Abstract: A group-III nitride based light emitter such as LED and LD, which has a double heterostructure and which comprises a diffusion suppressive layer between a p-type cladding layer and an active layer. The diode having a diffusion suppressive layer of the present invention has higher luminous intensity, greater forward voltage, and longer lifetime than the conventional diodes.Type: GrantFiled: August 28, 1996Date of Patent: August 11, 1998Assignee: Mitsubishi Cable Industries, Ltd.Inventors: Youichiro Ohuchi, Hiroaki Okagawa, Shinichi Watabe, Kazuyuki Tadatomo
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Patent number: 5783844Abstract: An optical semiconductor device includes an optical semiconductor element, a semiconductor region, and a buried layer. The optical semiconductor element is formed on a semiconductor substrate. The semiconductor region opposes the optical semiconductor element and essentially surrounds the optical semiconductor element to form walls. The buried layer is arranged between the walls of the semiconductor region and the optical semiconductor element and formed by vapor phase epitaxy. In this optical semiconductor device, a distance between the wall of the semiconductor region and a side wall of the optical semiconductor element is larger in a portion in which the growth rate of the vapor phase epitaxy in a horizontal direction from the side wall of the optical semiconductor element and the wall of the semiconductor region is higher.Type: GrantFiled: September 27, 1995Date of Patent: July 21, 1998Assignee: Nippon Telegraph and Telephone CorporationInventors: Fumihiko Kobayashi, Takeo Miyazawa, Hidefumi Mori, Jun-ichi Nakano
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Patent number: 5710463Abstract: A high-voltage breakover diode is proposed, which takes on the function of an ignition voltage distributor of an internal combustion engine having solid-state highvoltage distribution. The high-voltage breakover diode comprises a cascade of breakover diode chips, a polyimide layer having recesses in the region of the cathode connection being provided between the individual breakover diode chips produced using planar technology, in each case on the top of the breakover diode chips, and the mechanical and electrical connection of the individual breakover diode chips being effected by means of a conductive adhesive (FIG. 3).Type: GrantFiled: January 17, 1996Date of Patent: January 20, 1998Assignee: Robert Bosch GmbHInventors: Manfred Vogel, Johann Konrad, Werner Herden, Richard Spitz, Herbert Goebel