Abstract: A chip package device comprises on its outside surface a plurality of wire bonding electrodes adjacent a plurality of facedown electrodes. The chip package device comprises an IC chip having a plurality of chip electrodes on its face surface and a contact sheet having an inside surface on the face surface and comprising on the outside surface a plurality of conductor patterns which comprises portions extending through the contact sheet to the chip electrodes, respectively, and defines the facedown and the wire bonding electrodes. Such chip package devices can be mounted on a printed circuit board in whichever of a facedown and a wire bonding manner when primary and secondary pads are formed on the board for mechanical and electrical connection to the facedown electrodes, respectively, and for electric connection by bonding wires to the wire bonding electrodes, respectively.

Abstract: A semiconductor device includes a plastic substrate with a multilayer structure having electrically conductive lines and an embedded planar metal layer, a semiconductor chip having electrodes connected to respective lines by solder, and a sealing member of a synthetic resin adhering the semiconductor chip tightly to the plastic substrate.

Abstract: A semiconductor device having metal wirings in two or more layers has a slit formed in the metal wiring which is a lower layer, and a SOG film flows into the slit while forming the SOG film. The film thickness of the SOG film formed on the metal wiring of a large area differs little from that of the SOG film formed on the metal wiring of a small area. Therefore, a grade of flatness of an interlayer insulating film disposed between the metal wirings is not deteriorated. A humidity resistant property and an electromigration resistant property are not degraded.

Abstract: A light emitting diode for generating preferably green light with improved luminous efficiency. A number of epitaxial layers suitable for the light emission is arranged on a doped semiconductor substrate wafer of GaP. The surface of the epitaxial layers is completely frosted. The light emission from the interior is considerably improved by the frosting. A contact layer structure is placed on the frosted surface for contacting the light emitting diode. The contact layer consists of several partial layers and covers at least a part the frosted surface. There is also a contact layer at the rear of the light emitting diode.

Abstract: Ends of inner leads are disposed in the vicinity of a peripheral end of a semiconductor chip and a portion of an insulating film tape is affixed to a main surface of the semiconductor chip by an adhesive while other portions of the insulating film tape are affixed to portions of the inner leads by an adhesive. Electrode pads provided in the main surface of the semiconductor chip are electrically connected to the ends of the corresponding inner leads by bonding wires, and the semiconductor chip, the inner leads, the electrode pads, the insulating film tape and the bonding wires are sealed by a resin molding. The thickness of the insulating film tape is smaller than a height from the main surface of the semiconductor chip to an apex of the bonding wire. Surfaces of the ends of the inner leads connected to the bonding wires are positioned lower than the main surface of the semiconductor chip and the inner leads are positioned between the main surface and an opposite surface of the semiconductor chip.

Abstract: High density heatsinks for microcircuit packages are formed by first mold-pressing a composite powder of free-flowing spray-dried particles of an inexpensive high thermal conductivity material having a high coefficient of thermal expansion (CTE) such as copper and at least one other low CTE material such as tungsten, the proportions of which are adjusted to match the CTE of the microcircuit material. The pressed compacts are sintered in order to achieve an homogeneous distribution of the melting copper throughout the structure. A multilevel embodiment of the heatsink comprises two bonded layers of metals or composites having their coefficients of thermal expansion adjusted to match those of the semiconductor material and of any supporting structures respectively, wherein the second layer in contact with the supporting structure has a high CTE and the other has a lower CTE.

Abstract: A chip scale ball grid array for integrated circuit packaging having a nonpolymer layer or support structure positioned between a semiconductor die and a substrate. The nonpolymer support structure acts to increase circuit reliability by reducing thermal stress effects and/or by reducing or eliminating formation of voids in an integrated circuit package. A nonpolymer support structure may be a material, such as copper foil, having sufficient rigidity to allow processing of chip scale package in strip format.

Abstract: This invention is related to a metallization of Cu.The semiconductor device comprises a first insulating layer having a groove in a surface thereof, a second insulating layer on a surface of the groove, made of a material having a low density of crystal defects in comparison with that of the first insulating layer, and a wiring layer buried in the groove, surrounded by the second insulating layer.

Abstract: Disclosed is a semiconductor device comprising an integrated circuit chip, a first lead having a portion extending substantially in parallel to one side plurality of the chip, and a second lead located adjacent to the first lead. Each of the first and second leads has a recess and a projection continuously. The first lead and second lead are arranged adjacent to each other with the recess and projection of the first lead being in engagement with the projection and recess of the second lead. Bonding wires are bonded on the projection of the first lead and the projection of the second lead. The bonding wires electrically connect the chip to the first lead and also to the second lead.

Abstract: A gallium nitride type compound semiconductor light emitting element, such as a semiconductor laser, a light emitting diode is constructed by forming an In.sub.0.06 Ga.sub.0.94 N buffer layer, an n-type In.sub.0.06 Ga.sub.0.94 N clad layer, an n-type In.sub.0.06 Al.sub.0.15 Ga.sub.0.79 N clad layer, an undoped GaN active layer having layer thickness of 50 nm, a p-type In.sub.0.06 Al.sub.0.15 Ga.sub.0.79 N clad layer and a p-type In.sub.0.06 Ga.sub.0.94 N cap layer on a (0001) azimuth sapphire substrate. A p-side electrode is formed on the p-type In.sub.0.06 Ga.sub.0.94 N cap layer, and an n-side electrode is formed on the n-type In.sub.0.06 Ga.sub.0.94 N clad layer. In the construction set forth above, a greater thickness for the active layer is provided. Also, tensile strain is applied to the active layer. Light is taken out in parallel direction to the substrate. This threshold current of the semiconductor laser is lowered and light emitting efficiency of the light emitting diode is improved.

Abstract: Two modules, each of which has a plurality of memory IC chips installed therein, are stacked to form a module unit. Furthermore, a plurality of the module units are installed on a mother board so as to form a multilevel semiconductor integrated circuit device. By further stacking a specific module containing an IC chip for replacing the functions of a defective chip, a repair process can be conducted more easily and efficiently. Alternatively, instead of the module units, a plurality of TAB packages stacked in a multilayer structure are installed on the mother board. Outer leads of each of the TAB packages and terminal pads on the circuit board are respectively connected to each other in a one-to-one way. Thus, only a defective TAB package need be taken away and consequently, efficiency in the repair process further improves.

Abstract: A semiconductor device (30) includes a bumped semiconductor die (32) having a plurality of input/output (I/O) bumps (36) and a plurality of alignment bumps (38). Alignment bumps (38) are formed at the same time as I/O bumps (36) and are used by a vision system to properly align die (32) to a mounting substrate (34) for attachment thereto. Because the alignment bumps are smaller than the I/O bumps, the alignment bumps are not damaged during manufacturing operations such as wafer probe, burn-in, or test, and therefore maintain their original shape. The vision system can thus use the alignment bumps to repeatedly and accurately align the die to the mounting substrate, thereby eliminating misalignment caused by damage to the I/O bumps.

Abstract: The present invention is a semiconductor device comprising a semiconductor layer of SiC, a metal layer adapted to form a low resistance ohmic contact with the SiC-layer and a thin layer of a material having a smaller bandgap than the SiC of the SiC-layer and is placed between the SiC-layer and the metal layer. The SiC-layer is highly doped at least in the region next to the thin layer, and the material of the thin layer is a Group 3B-nitride including indium and at least another Group 3B-element.

Abstract: A molecular beam epitaxy (MBE) system (10) is provided to grow thin film, epitaxy layers (44, 46, 48, 50) on compound semiconductor substrates (40). A mass spectrometer detector (95) is used to monitor and control the flux from selected sources (21, 23, 25, 27) within the MBE system (10). A uniform layer of indium gallium arsenide (46, 50) may be grown on a semiconductor substrate (40) by controlling the indium flux with respect to substrate (40) temperature and time. An epitaxy layer (46) of indium gallium arsenide with uniform mole fraction concentration and reduced lattice strain is produced.

Abstract: A dual channel field-effect switching device is disclosed. The switching device includes two adjacent semiconductor regions of opposite polarity forming a PN junction therebetween. A gate structure overlying the semiconductor regions controls the presence of two electrically isolated conductive channels formed in selected portions of the semiconductor regions.

Abstract: This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements.

Abstract: After forming a gate oxide film on the surface side of a single crystalline silicon substrate, a first polycrystalline silicon layer is subsequently formed. After that, portions of polycrystalline silicon layers are left in each gate electrode formation region of a high voltage drive circuit. Then, the gate oxide film in a low voltage drive circuit side is removed while maintaining this state. Then, after forming a gate oxide film on those surface sides, a polycrystalline silicon layer is subsequently formed in the surface side. After that, impurities are introduced into the polycrystalline silicon layer to provide it with electrical conduction, and then portions of polycrystalline silicon layers are left.

Abstract: A heterostructure laser diode is provided with an active region that includes a ternary or quaternary semiconductor compound. The composition of the semiconductor compound forming the active region is modulated resulting in an active region with a modulated strain profile (.increment.a/a), e.g., a triangular sawtooth-like strain profile, perpendicular to the laser diodes epitaxial layers, i.e., parallel to the z-axis. This permits the present invention to increase strain and avoid formation of misfit dislocations by compensation, i.e., by inserting strained layers having opposing strains.

Abstract: A temperature sensor is monolithically integrated in a semiconductor body together with a vertical power semiconductor structure. The power semiconductor structure is formed of a plurality of power cells. The temperature sensor is formed of two sensor cells that can be manufactured simultaneously with the power cells. The advantage of the invention is that a highly sensitive temperature sensor can be manufactured in process-compatible fashion together with a vertical power semiconductor structure without additional steps and in a cost-beneficial way.