Abstract: According to one embodiment, an information processing apparatus includes an information processing apparatus main body and a storage drive which is accommodated in the information processing apparatus body. The information processing apparatus main body includes a main control module which controls power activation of the storage drive based on a power activation operation by a power operation section. The storage drive includes a storage memory including a plurality of storage areas to and from which information can be written and read, a counter in which a count is incremented upon power activation, and a memory control module which stores a content of an access request in a storage area of the storage memory determined based on the count of the counter when the access request to the storage memory is made.

Abstract: A data storage system can automatically improve the layout of data blocks on a mass storage subsystem by collecting optimization information during both read and write activities, then processing the optimization information to limit the impact of optimization activities on the system's response to client requests. Processing read-path optimization information and write-path optimization information through shared rate-limiting logic simplifies system administration and promotes phased implementation, which can reduce the difficulty of developing a self-optimizing storage server.

Abstract: To maintain reliability even when the repetition of the power saving control for storage systems occurs frequently due to the access from the host computer. During the course of controlling the operation mode of the drives, the controller measures the start/stop cycle count and the load/unload cycle count, calculates the S/S wear-out rate showing the ratio of the measured value of the start/stop cycle count to the first upper limit value and the L/U wear-out rate showing the ratio of the measured value of the load/unload cycle count to the second upper limit value, and for the drives in the idle operation mode, selects the low-speed rotation operation mode if the S/S wear-out rate is greater than the L/U wear-out rate, or selects the standby operation mode if the S/S wear-out rate is less than the L/U wear-out rate.

Abstract: A system comprises a plurality of storage systems, which provides different storage functions, and is controlled by a management server. The management server determines whether to change the control of the storage controller between the storage systems, or to mount the target volume as an external volume and keep the storage controller under control so that the storage function provided to the source volume is maintained even after the configuration change between the storage systems. After the determination, the management server instructs the storage system to perform according to the determination.

Abstract: A data reception system includes a data acquisition unit acquiring data from a predetermined transmission path, an access control unit storing the data acquired by the data acquisition unit in a predetermined storage area, and a plurality of storage areas. The plurality of storage areas includes a first storage area and a second storage area having a greater storable capacity and a lower storing speed compared to the first storage area. The access control unit further includes a transfer unit. The access control unit determines whether the total amount of data stored in the first storage area is in the excess of a predetermined threshold or not and causes a transfer unit to transfer the data acquired by the data acquisition unit to the second storage area to store the data in the second storage area when the total amount is in the excess of the threshold.

Abstract: A computer-implemented method for defragmenting virtual machine prefetch data. The method may include obtaining prefetch information associated with prefetch data of a virtual machine. The method may also include defragmenting, based on the prefetch information, the prefetch data on physical storage. The prefetch information may include a starting location and length of the prefetch data on a virtual disk. The prefetch information may include a geometry specification of the virtual disk. Defragmenting on physical storage may include placing the prefetch data contiguously on physical storage, placing the prefetch data in a fast-access segment of physical storage, and/or ordering the prefetch data according to the order in which it is accessed at system or application startup.

Abstract: A directory and members are allocated to store a data set, wherein the directory stores pointers to the members to allow data stored in the members to be accessed. The directory is expanded to accommodate an expansion of the data set, causing the directory to be stored in non-contiguous pages and becoming fragmented. A computational device determines that a threshold that measures a level of fragmentation of the directory relative to an amount of storage allocated for the data set has been exceeded. The computational device reorganizes the fragmented directory, into a reorganized directory that is stored in contiguous pages at the end of the data set, in response to determining that the threshold has been exceeded.

Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.

Abstract: A device may receive requests intended for a memory that includes a number of banks, determine a number of the requests intended for each of the banks, determine an order for the requests based on the determined number of the requests intended for each of the banks, and send one of the requests to the memory based on the determined order.

Abstract: A system and method to trigger synchronization and validation actions at memory access, in one aspect, identifies a storage class associated with a region of shared memory being accessed by a thread, determines whether the thread holds the storage class and acquires the storage class if the thread does not hold the storage class, identifies a programmable action associated with the storage class and the thread, and triggers the programmable action. One or more storage classes are respectively associated with one or more regions of shared memory. An array of storage classes associated with a thread holds one or more storage classes acquired by the thread. A configurable action table associated with a thread indicates one or more programmable actions associated with a storage class.

Abstract: The present invention calculates the power consumption of the storage system for each device which supplies power with a storage system, and controls the storage system to keep the power consumption not to exceed the upper limit. In order to achieve this, the power consumption of the chassis configuring the destination storage system is calculated with reference to the number of logical volumes configuring the pool which includes virtual logical volumes, and the logical volumes included in the source storage system are migrated to the virtual logical volumes included in the destination storage system, keeping the power consumption specified in advance per device supplying power to the chassis configuring the destination storage system not to exceed the upper limit value. (Refer to FIG. 27.

Abstract: Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.

Abstract: In a semiconductor storage device, a memory controller divides each of blocks in each of chips into a first page set composed of pages and a second page set composed of pages, divides a logical address space into groups, and divides each group into lines. Block units are created each of which is obtained by assembling a predetermined number of blocks from the blocks in each chip. A predetermined number of block units from the block units are managed as standard block units, and the other block units are managed as spare block units. Each standard block unit is made to correspond to one group. The corresponding group data is stored in the pages in the first page set in each block constituting the standard block unit, and unwritten pages for recording update data for the group data are provided to be included in the second page set.

Abstract: Hybrid caching techniques and garbage collection using hybrid caching techniques are provided. A determination of a measure of a characteristic of a data object is performed, the characteristic being indicative of an access pattern associated with the data object. A selection of one caching structure, from a plurality of caching structures, is performed in which to store the data object based on the measure of the characteristic. Each individual caching structure in the plurality of caching structures stores data objects has a similar measure of the characteristic with regard to each of the other data objects in that individual caching structure. The data object is stored in the selected caching structure and at least one processing operation is performed on the data object stored in the selected caching structure.

Abstract: The present invention discloses a memory system having a hybrid density memory. The memory system includes a plurality of storage spaces whereby the storage spaces have respective levels of endurance and each storage space has a plurality of blocks and pre-determined weighting factors corresponding to the levels of endurance of the storage spaces. After executing a command of erasing a specific block, the system records the erase in accordance with the weighting factor of the storage space to which the specific block belongs. Whereby, the erase counts of all the blocks of different storage spaces are able to reach respective levels of endurance as simultaneously as possible.

Abstract: A device includes a memory that includes a number of banks. The device receives requests for accessing the memory, determines the banks to which the requests are intended, determines one or more of the banks that are available, selects one or more of the requests to send to the memory based on the one or more of the banks that are available and have a request to be serviced, and sends the selected one or more requests to the memory.

Abstract: A method and apparatus for allocating storage addresses are disclosed. The method includes: receiving a storage address allocation request; searching a level-2 bitmap in a hierarchical bitmap in bidirectional mode; outputting an idle bit according to the result of searching in the level-2 bitmap; obtaining a storage address according to the output idle bit, and allocating the storage address. The apparatus includes: a first receiving module, configured to receive a storage address allocation request; a first searching module, configured to search a level-2 bitmap in a hierarchical bitmap in bidirectional mode for an idle bit, wherein the hierarchical bitmap includes N level-1 bitmaps and the level-2 bitmap; and an allocating module, configured to: obtain a storage address according to the output idle bit in the level-2 bitmap, and allocate the obtained storage address.

Abstract: A method of selecting a target volume in a storage system is provided. The method comprises defining one or more parameters for a plurality of storage volumes in the storage system according to user preference; dynamically collecting information related to the parameters while the storage volumes are used; receiving a request to backup a first source volume in the storage system; and selecting or creating the target volume based on the collected information.

Abstract: Call stack protection, including executing at least one application program on the one or more computer processors, including initializing threads of execution, each thread having a call stack, each call stack characterized by a separate guard area defining a maximum extent of the call stack, dispatching one of the threads of the process, including loading a guard area specification for the dispatched thread's call stack guard area from thread context storage into address comparison registers of a processor; determining by use of address comparison logic in dependence upon a guard area specification for the dispatched thread whether each access of memory by the dispatched thread is a precluded access of memory in the dispatched thread's call stack's guard area; and effecting by the address comparison logic an address comparison interrupt for each access of memory that is a precluded access of memory in the dispatched thread's guard area.

Abstract: This invention, in the interface coupled to the server, the disk interface coupled to the second memory to store final data, the cache to store data temporarily, and in the storage system with the MP which controls them, specifies the area by referring to the stored data, and makes the virtual memory area resident in the cache by using the storage system where the specified area is made resident in the cache.