Abstract: An approach for deleting a file from a primary file system. The approach deletes a directory entry, associated with a file, from an in-memory index associated with a secondary file system. The approach updates an index cache associated with a secondary file system, based on the in-memory index. The approach updates a dirty flag, associated with the secondary file system, to a value of TRUE.

Abstract: Configurable variable-length shift register circuits include a group of flip-flops connected in a serial configuration. The plurality of flip-flops is connected to a serial data-in line and a clock line. Each flip-flop can include a data input, a clock input configured to receive a clock signal from the clock line, and a data output. The plurality of flip-flops can include a serial data-out line. The circuit includes a plurality of multiplexers connected to the plurality of flip-flops to enable a desired number of flip-flops for an application. A nonvolatile memory can be connected to the plurality of multiplexers and configured to receive a register-length indication, where the register-length indication corresponds to a selected number of flip-flops selected for enablement for a given application.

Abstract: Various implementations described herein relate to systems and methods for managing superblocks, including a non-volatile storage including a superblock and a controller configured to notify a host of a size of the superblock to a host, determine a stream that aligns with the superblock, write data corresponding to the stream to the superblock, and determine that writing the data correspond to the stream has completed.

Abstract: Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct another die to execute a memory operation while the first die is in the wait state. In response to receiving a second type of program execution command from the memory controller when in the wait state, the first die will program the data into non-volatile memory cells. The memory controller may issue the second type of program execution command in response to determining that sufficient power resources (or thermal budget) exist.

Abstract: Aspects of the disclosure are directed to hardware interconnects and corresponding devices and systems for non-coherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device.

Abstract: A method for managing a memory associated with PCIe SSD including: generating memory pools of equal size from a predefined size of contiguous physical memory, each of the memory pools manages a memory request of different size and is associated with a respective predefined size of memory request; dividing each of the memory pools into first set of memory pages, each having a size equal to maximum size among the predefined size of the memory request associated with the respective memory pool; dividing each of the first set of memory pages into second set of memory pages, each having a size equal to the predefined size of the memory request associated with respective memory pool; and managing the contiguous physical memory by allocating a memory page from the second set of memory pages fora memory request corresponding to the size of the second set of memory pages.

Abstract: An apparatus to facilitate in-place memory copy during remote data transfer in a heterogeneous compute environment is disclosed. The apparatus includes a processor to receive data via a network interface card (NIC) of a hardware accelerator device; identify a destination address of memory of the hardware accelerator device to write the data; determine that access control bits of the destination address in page tables maintained by a memory management unit (MMU) indicate that memory pages of the destination address are both registered and free; write the data to the memory pages of the destination address; and update the access control bits for memory pages of the destination address to indicate that the memory pages are restricted, wherein setting the access control bits to restricted prevents the NIC and a compute kernel of the hardware accelerator device from accessing the memory pages.

Abstract: Provided is an operating method of a storage device. The method includes providing temperature information of each of a plurality of volatile memory devices in the storage device to a host device; and receiving a setting command related to a refresh operation of the plurality of volatile memory devices from the host device, wherein the plurality of volatile memory devices are classified into groups based on temperature information, and wherein the setting command indicates a number of rows of the plurality of volatile memory devices to be refreshed differently for each of the groups based on the temperature information.

Abstract: Technologies are described for cost based management of cache entries stored in a computer memory. In one example, a plurality of cache entries may be stored at a cache in a computer memory and the cache entries may have a cost measure associated with individual cache entries. A cost measure may represent a computing cost of an application to generate a cache entry. An incoming cache entry may be received at the cache, where the incoming cache entry has a cost measure associated with the incoming cache entry. In response to receiving the incoming cache entry, a cache entry that has a lower cost measure than the cost measure for other cache entries may be identified for eviction from the cache. The cache entry identified for eviction may be evicted from the cache, and the incoming cache entry may be written into the cache stored in the computer memory.

Abstract: A method for tracking open blocks in a memory device includes partitioning, by a memory sub-system controller, a storage region in the memory device into a plurality of channels, each channel including a plurality of planesets, and each planeset comprising a plurality of blocksets. The method further includes distributing evenly between the plurality of channels a plurality of active zones ready for a write operation. Each active zone includes one or more open blocks. The method further includes sending, by the memory sub-system controller, an open block message to a controller in the memory device, the open block message including channel identifying information, planeset identifying information, and blockset identifying information. The channel identifying information, the planeset identifying information, and the blockset identifying information collectively identify one or more open blocks ready for a write operation in the memory device.

Abstract: A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.

Abstract: An example system includes a memory, a processor in communication with the memory, and a supervisor. The supervisor is configured to allocate a memory space in the memory to a workload executing on the processor. The supervisor is configured to store data written by the workload as dirty memory in the memory space at least until the data is written back to a data storage. Based on a type of the workload being a first type, the supervisor is configured to trigger write back of at least a portion of the dirty memory into the data storage in response to the dirty memory exceeding a threshold level. Based on the type of the workload being a second type, the supervisor is configured to delay write back of the dirty memory into the data storage in response to the dirty memory exceeding the threshold level.

Abstract: An apparatus comprising a cache comprising a plurality of cache entries, cache access circuitry responsive to a cache access request to perform, based on a target memory address associated with the cache access request, a cache lookup operation, tracking circuitry to track pending requests to modify cache entries of the cache, and prediction circuitry responsive to the cache access request to make a prediction of whether the pending requests tracked by the tracking circuitry include a pending request to modify a cache entry associated with the target memory address, wherein the cache access circuitry is responsive to the cache access request to determine, based on the prediction, whether to perform an additional lookup of the tracking circuitry. A method and a non-transitory computer-readable medium to store computer-readable code for fabrication of the apparatus are also provided.

Abstract: Methods, systems, and devices for command block management are described. A memory device may receive a command (e.g., from a host device). The memory device may determine whether the command is defined by determining if the command is included within a set of defined commands. In the case that a received command is absent from the set of defined commands (e.g., the command is undefined), the memory device may block the command from being decoded for execution by the memory device. In some cases, the memory device may switch from a first operation mode to a second operation mode based on receiving an undefined command. The second operation mode may restrict an operation of the memory device, while the first mode may be less restrictive, in some cases. Additionally or alternatively, the memory device may indicate the undefined command to another device (e.g., the host device).

Abstract: A client device including at least one memory configured to be used at least in part as a shared cache in a distributed cache. A network interface of the client device is configured to communicate with one or more other client devices on a network with each of the one or more other client devices configured to provide a respective shared cache for the distributed cache. At least one processor of the client device is configured to execute a kernel of an Operating System (OS) for allocating resources of the client device. The kernel is configured to access data for the distributed cache in the shared cache, which is located in a kernel space of the at least one memory.

Abstract: A controller is provided. The controller includes a write queue configured to store commands for operating a memory device that are generated based on requests received from a host, zone identifications of the commands each indicating a memory region in the memory device to store data corresponding to a command, and write pointers of the commands each indicating an order that the requests are output from the host; and a queue controller configured to receive the commands, the zone identifications, and the write pointers from the write queue, store the commands in buffers allocated the zone identifications based on the write pointers, respectively, and based on an occurrence of an event that a number of commands stored in a buffer among the buffers reaches a preset number set in the buffer, output commands stored in the buffer.

Abstract: Embodiments herein described a coherency protocol for a distributed computing topology that permits for large stalls on various interfaces. In one embodiment, the computing topology includes multiple boards which each contain multiple processors. When a particular core on a processor wants access to data that is not currently stored in its cache, the core can first initiate a request to search for the cache line in the caches for other cores on the same processor. If the cache line is not found, the cache coherency protocol permits the processor to then broadcast a request to the other processors on the same board. If a processor on the same board does not have the data, the processor can then broadcast the request to the other boards in the system. The processors in those boards can then search their caches to identify the data.

Abstract: According to one embodiment, a controller writes a first data associated with a write request and a first logical address specified by the write request to a first block. The controller updates a logical-to-physical address translation table such that a first physical address indicating a first storage location in the first block in which the first data is written is associated with the first logical address. In response to receiving an invalidation request for invalidating the first data corresponding to the first logical address, the controller acquires, from the logical-to-physical address translation table, the first physical address, and updates a valid data identifier corresponding to a storage location indicated by the first physical address to a value indicating invalidation.

Abstract: Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.

Abstract: Redo logs are used to facilitate efficient cloning of virtual machines. When a virtual machine with a virtual hard disk is to be cloned, two redo logs are created, both of which are linked to the virtual hard disk. The virtual machine being cloned is then linked to one redo log, and a newly created virtual machine is linked to the other. Each time an additional virtual machine is created, two new redo logs are created and linked to the end of the disk chain. The parent and newly created virtual machine are each linked to one of the new redo logs.