Patents Examined by Neah Berezny
  • Patent number: 6090648
    Abstract: A method of making a self-aligned, integrated resistor load on ultrathin silicon on sapphire film, with the method being used to manufacture an FET and a resistor load. While the film can be used, for example, to manufacture a four transistor SRAM, it is not limited to such applications. The method encompasses an integral resistor load which can be integrated with analog components or formed as part of an integrated circuit for electrostatic discharge (ESD) circuitry, or the like. The resistor load can be integrally formed from the same silicon island which forms a corresponding transistor. Because the resistor load can be made from, and integral with, the ultra thin silicon material, it can be automatically self-aligned to the transistor. The self-aligned, integrated resistor loads are comprised of an insulating substrate, with a layer of silicon formed on the insulating substrate.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: July 18, 2000
    Assignee: Peregrine Semiconductor Corp.
    Inventors: Ronald E. Reedy, Mark L. Burgener