Abstract: A method of fabricating an array substrate includes forming a first metal layer, a gate insulating material layer and an oxide semiconductor material layer on a substrate; heat-treating the substrate having the oxide semiconductor material layer at a temperature of about 300 degrees Celsius to about 500 degrees Celsius; patterning the oxide semiconductor material layer, the gate insulating material layer and the first metal layer, thereby forming a gate electrode, a gate insulating layer and an oxide semiconductor layer; forming a gate line connected to the gate electrode and made of low resistance metal material; forming source and drain electrodes, a data line and a pixel electrode, the source and drain electrodes and the data line having a double-layered structure of a transparent conductive material layer and a low resistance metal material layer, the pixel electrode made of the transparent conductive material layer.

Abstract: To improve quality or manufacturing throughput of a semiconductor device, a method includes supplying a source gas to a substrate in a process chamber; exhausting an inside of the process chamber; supplying a reaction gas to the substrate; and exhausting the inside of the process chamber, wherein the source gas and/or the reaction gas is supplied in temporally separated pulses in the supply of the source gas and/or in the supply of the reaction gas. Then, the source gas and/or the reaction gas is supplied in temporally separated pulses to form a film during a gas supply time determined by a concentration distribution of by-products formed on a surface of the substrate.

Abstract: A pixel structure and a method of manufacturing a pixel structure are provided. The pixel structure includes an active device, a gate insulation layer, a dielectric insulation layer, a capacitance electrode, a protection layer and a pixel electrode. The active device includes a gate, a semiconductor channel layer, a source and a drain. The dielectric insulation layer covers the semiconductor channel layer. A dielectric index of the dielectric insulation layer is greater than a dielectric index of the gate insulation layer. The capacitance electrode is overlapped with the drain. The capacitance electrode, the drain and the dielectric insulation layer between the two constitute a storage capacitor structure. The protection layer is disposed on the dielectric insulation layer and the capacitance electrode is located between the protection layer and the dielectric insulation layer. The pixel electrode is disposed on the protection layer and connected to the drain of the active device.

Abstract: A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.

Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

Abstract: The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region.

Abstract: Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided.

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract: A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.

Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.

Abstract: A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.

Abstract: Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

Abstract: An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer.

Abstract: A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a glue material, next forming a polymer material on the substrate, on the semiconductor chip, and on the metal bump, next polishing the polymer material, next forming a patterned circuit layer over the polymer material and connected to the metal bump, and then forming a tin-containing ball over the patterned circuit layer and connected to the patterned circuit layer.

Abstract: A method for forming thin film solar cell materials introducing a first inert gas mixture that includes hydrogen selenide into a chamber at a first pressure value until the chamber reaches a second pressure value and at a first temperature value, wherein the second pressure value is a predefined percentage of the first pressure value. The temperature in the chamber is increased to a second temperature value for a selenization process so that the pressure in the chamber increases to a third pressure value. Residual gas that is generated during the selenization process can be removed from the chamber. A second inert gas mixture that includes hydrogen sulfide is added into the chamber until the chamber reaches a fourth pressure value. The temperature in the chamber is increased to a third temperature value for a sulfurization process. The chamber is cooled after the sulfurization process.

Abstract: Various embodiments include resistor structures. Particular embodiments include a resistor structure having multiple oxide layers, at least one of which includes a modified oxide. The modified oxide can aid in controlling the thermal capacitance and the thermal time constant of the resistor structure, or the thermal dissipation within the resistor structure.