Patents Examined by Nitin C. Patel
  • Patent number: 11966756
    Abstract: The present disclosure generally relates to dataflow applications. In aspects, a system is disclosed for scheduling execution of feature services within a distributed data flow service (DDFS) framework. Further, the DDFS framework includes a main system-on-chip (SoC), at least one sensing service, and a plurality of feature services. Each of the plurality of feature services include a common pattern with an algorithm for processing the input data, a feature for encapsulating the algorithm into a generic wrapper rendering the algorithm compatible with other algorithms, a feature interface for encapsulating a feature output into a generic interface allowing generic communication with other feature services, and a configuration file including a scheduling policy to execute the feature services. For each of the plurality of feature services, processor(s) schedule the execution of a given feature service using the scheduling policy and execute a given feature service on the standard and/or accelerator cores.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: April 23, 2024
    Assignee: Aptiv Technologies AG
    Inventors: Vinod Aluvila, Miguel Angel Aguilar
  • Patent number: 11960250
    Abstract: A main circuit includes a switching element, and converts electric power input to the main circuit and supplies a result of the conversion to a load. The controller switches a control scheme of the main circuit from a first control scheme to a second control scheme at a first time point when the output value starts to vary and switches the control scheme of the main circuit from the second control scheme to the first control scheme at a second time point when a determination is made that switching of a variation direction of the output value will occur on the basis of a detection value of the detector.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: April 16, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shota Watanabe, Tomokazu Sakashita
  • Patent number: 11954504
    Abstract: Disclosed herein are system, method, and computer program product embodiments for a method of cloud infrastructure optimization. The method identifies an existing infrastructure configuration deployed in a cloud environment and generates a plurality of proposal configurations, each of the plurality of proposal configurations having executable code configured to adjust the existing infrastructure configuration for at least one variable. The method selects a proposal configuration from the plurality of proposal configurations based on the at least one variable adjusted for in the existing infrastructure configuration, and the selected proposal configuration is deployed in the cloud environment. The method then analyzes the selected proposal configuration for a level of adjustment for the at least one variable. The method trains a model engine with existing and new training data.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: April 9, 2024
    Assignee: Capital One Services, LLC
    Inventors: Daniel Vincent Safronoff, Ron Meck, James Hounshell, Eric Schultz
  • Patent number: 11947382
    Abstract: A known randomized data pattern at a predetermined reference voltage of the internal oscilloscope is inputted to an internal oscilloscope of the receiving device for each delay tap element of a plurality of consecutive delay tap elements applied to a system clock of a receiving device. A first delay tap element among the plurality of consecutive delay tap elements in which an output of the internal oscilloscope matches the known randomized data pattern is identified. Responsive to identifying the first delay tap element, a last delay tap element among the plurality of consecutive delay tap elements in which the output of the internal oscilloscope matches the known randomized data pattern is identified.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Brandon Richard Nixon
  • Patent number: 11947405
    Abstract: A rack in a datacenter is powered by a first power feed and a second power feed. The rack supports a plurality of servers which have a maximum combined power consumption which is greater than a maximum supplied power from either the first power feed or the second power feed. When power is lost from one of the power feeds, a rack manager reduces the total power consumption of the plurality of servers by throttling at least one of the servers and/or shutting off at least one of the plurality of servers.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: April 2, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kyle Edward Woolcock, Alok Gautam Kumbhare, Nithish Mahalingam, Brijesh Warrier
  • Patent number: 11934246
    Abstract: Object Provided is a power supply device and the like capable of improving convenience. Solving means A power supply device according to an embodiment of the present disclosure include a power supply unit that supplies power to an electromedical device, a first impedance control unit disposed on a path of a circulation path of the power between the power supply unit and the electromedical device, excluding an input path for inputting an electrical signal obtained in the electromedical device to another device, and a second impedance control unit disposed on the input path of a path between the power supply unit and the other device. An impedance state of each of the first and second impedance control units transitions in accordance with a supply state of the power to the electromedical device.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: March 19, 2024
    Assignee: JAPAN LIFELINE CO., LTD.
    Inventors: Hisao Miyamoto, Yusuke Oshima
  • Patent number: 11915009
    Abstract: Disclosed are a method, an apparatus, and a non-transitory computer-readable storage medium for obtaining applications. The method includes: identifying an external device connected to an interface according to states of pins of the interface; identifying applications which require to use the external device connected to the interface; and displaying at least one of the applications identified.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: February 27, 2024
    Assignee: ZTE CORPORATION
    Inventor: Duo Gao
  • Patent number: 11914417
    Abstract: A memory is provided. The memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: February 27, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Shu-Liang Ning, Jun He, Zhan Ying, Jie Liu
  • Patent number: 11914418
    Abstract: A data acquisition system and a control method, apparatus, and device therefor, and a medium. The data acquisition system comprises: a signal transmission line, the signal transmission line having multiple first signal delay units connected in series, and the output end of each of the first signal delay units forming an acquisition point; multiple acquisition units, the acquisition units being connected to the acquisition points of the first signal delay units to acquire signals at the acquisition points; a clock unit, configured to generate a control signal; a comparison unit, configured to compare the period of the control signal with the period of a standard signal, and generate an adjustment signal according to the comparison result; and an adjustment unit, configured to adjust a power supply voltage for the signal transmission line and the clock unit according to the adjustment signal, so that the ratio of the period of the control signal to the period of the standard signal meets a set threshold range.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: February 27, 2024
    Assignee: Gree Electric Appliances, Inc. of Zhuhai
    Inventors: Jiangxun Tang, Qiao Huang, Yuqing Nie
  • Patent number: 11914445
    Abstract: An electronic device comprising a system on chip and an external module. The system on chip includes a plurality of internal subsystems and a power management system including a plurality of internal voltage regulators which supply power to the plurality of internal subsystems. Each of the internal voltage regulators has an associated current limiter. The external module includes at least one external voltage regulator which can provide power to at least one of the internal subsystems. The power management system during a start-up phase enables the internal voltage regulators and the current limiters and in a subsequent phase determines an externally powered set of the internal subsystems, disables the corresponding internal voltage regulators, and disables the current limiters associated with the internal subsystems not externally powered.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 27, 2024
    Assignee: Nordic Semiconductor ASA
    Inventors: Bartosz Gajda, Frode Pedersen
  • Patent number: 11907733
    Abstract: An example target device is described for facilitating application docking. In various aspects, the target device can comprise a processor. In various instances, the target device can comprise a non-transitory machine-readable memory that can store machine-readable instructions. In various cases, the processor can execute the machine-readable instructions, which can cause the processor to launch, based on a dock request that is to indicate a session of a first instance of an application of an initiator device, a second instance of the application on the target device. In various aspects, the second instance can resume the session. In various instances, the launch can be based on a determination that a dock credential of a Quick Response (QR) code generated by the target device is in the dock request.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: February 20, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Alexander Morgan Williams, Syed Azam
  • Patent number: 11899522
    Abstract: A system includes a memory device of multiple devices, and a processing device of the multiple devices, coupled with the memory device. The system identifies multiple device temperature values that are each indicative of a temperature at a respective device of the multiple devices of the system. The system determines that at least one device temperature value of the multiple device temperature values satisfies a respective thermal throttling threshold of multiple thermal throttling thresholds. The system performs a power reducing operation to reduce a power consumption of the system in accordance with a power reduction value based on the satisfaction of the respective thermal throttling threshold.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Curtis W. Egan
  • Patent number: 11899521
    Abstract: Methods and apparatus for performing timed functions in battery-powered, wireless electronic devices, such as sensors or control modules. Such electronic devices comprise a main processor and a co-processor. When the main processor enters a quiescent state in order to preserve battery life, one or more timed functions are transferred from the main processor to the co-processor just before the main processor enters the quiescent state. When the co-processor determines that it is time to perform the timed function, the co-processor wakes the main processor in order for the main processor to perform the timed function.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: February 13, 2024
    Assignee: Ecolink Intelligent Technology, Inc.
    Inventor: Brandon Gruber
  • Patent number: 11899491
    Abstract: The system and method generates a pulse or a signal that is transmitted between a central processing unit or processor and an Ethernet integrated circuit card to program a trigger generator in the IC. The pulse is effectively a 1PPS signal that is provided to the IC, which may be in the form a field programmable gate array to enable timing synchronization. The trigger in the IC may also generates an interrupt to the processor so a driver in the CPU is instructed to set the next trigger. For the trigger to be accurately controlled, the control routine is implemented in the driver existing in kernel space rather than user space. A routine or protocol periodically polls the interrupt to determine when the trigger must be reset.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: February 13, 2024
    Inventors: Matthew J. Sherman, Mritunjay Sinha, Lawrence Yang
  • Patent number: 11900129
    Abstract: An embodiment for improving a shutdown sequencing of a computer operating system (OS) is provided. The embodiment may include receiving a command to initiate an OS shutdown. The embodiment may also include creating a first list of running tasks to terminate. The embodiment may further include in response to determining there is no historical data, sending a termination request to a particular running task. The embodiment may also include in response to determining the particular running task requires user input to terminate, increasing a weight of the particular running task. The embodiment may further include in response to determining there is an additional particular running task in the created first list, sending the termination request to the additional particular running task. The embodiment may also include in response to determining the additional particular running task requires the user input to terminate, increasing the weight of the additional particular running task.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: February 13, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph Sayer, Benjamin David Cox, Andrew David Lyell
  • Patent number: 11899615
    Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Gerald Pasdast, Siva Soumya Eachempati, Tejpal Singh, Ankush Varma, Mahesh K. Kumashikar, Srikanth Nimmagadda, Carleton L. Molnar, Vedaraman Geetha, Jeffrey D. Chamberlain, William R. Halleck, George Z Chrysos, John R. Ayers, Dheeraj R. Subbareddy
  • Patent number: 11899523
    Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: February 13, 2024
    Assignee: Apple Inc.
    Inventors: Inder M. Sodhi, Achmed R. Zahir, Lior Zimet, Liran Fishel, Omri Flint, Ami Schwartzman
  • Patent number: 11886274
    Abstract: This application discloses a voltage scaling method and an electronic device. The method is applied to an electronic device having a processor and a power supply that supplies power to the processor. The method includes the processor sending power supply scaling information to the power supply based on an operating frequency in a next time period. The method further includes the power supply determining, based on the power supply scaling information, a supply voltage Vout used to supply power to the processor. The supply voltage Vout decreases as a load current of the power supply increases. Vmin?Vout?V, where Vmin is a lowest supply voltage of the processor at the operating frequency in the next time period, and V is a specified supply voltage of the processor at the operating frequency in the next time period.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: January 30, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhongjian Chen, Xiaokun Wang, Shibin Xu, Nianbing Li, Liangyi Zhang
  • Patent number: 11886268
    Abstract: In some examples, an electronic device comprises a battery; a storage device storing a user profile, the user profile comprising a usage pattern of the battery; and a processor coupled to the battery and the storage device, the processor to: receive a battery measurement of the battery and operational data of a first component of the electronic device; calculate a battery consumption of the first component based on the battery measurement; compare the battery consumption to the usage pattern; update, based on the comparison, the user profile using a time series model, wherein inputs to the time series model include the battery measurement and the operational data; and adjust a battery consumption of the electronic device based on the updated user profile.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: January 30, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Maikel Maciel Ronnau
  • Patent number: 11880259
    Abstract: The present disclosure relates to techniques for managing power assertions associated with applications that may run on an electronic device. For example, to reduce power consumption of power available on a power source of the electronic device, the electronic device may start a timer after receiving a request for a power assertion. When the timer expires, the electronic device may enter a low power state.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 23, 2024
    Assignee: Apple Inc.
    Inventors: Archana Venkatesh, Vaibhav Gautam, Ning Ding, Roberto Alvarez