Patents Examined by Njân V. Ngô
  • Digitline architecture for dynamic memory
    Patent number: 6661041
    Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F2 or smaller memory cells in a type of cross-point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: December 9, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Brent Keeth