Patents Examined by Norman Michael Wright
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Patent number: 5983362Abstract: A non-interrupted operation control apparatus for a modem is provided for the purpose of preventing communications errors caused by the corruption of control parameter data stored within the modem, and circuit hangs, wherein an initialization unit is provided for the purpose of periodically initializing the modem at prescribed time intervals during a period of no communications via the modem. The initialization unit performs resetting of the hardware and setting of control parameters anew at prescribed time intervals.Type: GrantFiled: May 23, 1997Date of Patent: November 9, 1999Assignee: Fujitsu LimitedInventors: Masaru Yasunaga, Takeshi Asahina, Shigeru Hashimoto
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Patent number: 5951696Abstract: Disclosed herein is sophisticated but low-cost debug hardware which may be used to identify the root cause of a functional or electrical problem in a microprocessor chip. The debug hardware provides for generating a hardware breakpoint trap (HBT) in response to programmed combinations of internal signal triggers, and if desired, a HBT may be delayed through one or more occurrences of a programmed trigger combination via use of an iteration counter. Apparatus for generating and handling a HBT may comprise one or more trigger means, one or more event generation means, and debug software comprising code for 1) preserving the current architected state of a microprocessor upon generation of a HBT, 2) vectoring to and initiating execution of trap handler code, and 3) restoring said preserved current architected state after said trap handler code has been executed.Type: GrantFiled: November 14, 1996Date of Patent: September 14, 1999Assignee: Hewlett-Packard CompanyInventors: Hosein Naaseh, Paul G. Tobin
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Patent number: 5925126Abstract: A security shield implementation method comprising computer software for use with a computer system's software which is transparent to the user of the computer system software and utilizes the steps of system call interception and interactive command interception to control access by a user of the computer system software. The system call interception for non-interactive commands, file access, programs, networks, and the interactive commands, such as access to interactive programs, are routed and examined by redirector software. Security rule checks and log event functions are then conducted on the non-interactive commands, file access requests, programs, networks, and the interactive commands. If a non-interactive command, file access request, program, network, or an interactive command is approved, the command request is then forwarded to the computer operating system.Type: GrantFiled: March 18, 1997Date of Patent: July 20, 1999Assignee: Memco Software, Ltd.Inventor: Vincent Hsieh
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Patent number: 5923843Abstract: A system for overriding access security in a computing device including a local security device and an input device. Access security is overridden when a medium containing override passcode information is inserted into an input device and the local security device reads and verifies the override passcode information. Alternatively, a second, remotely located security device reads and verifies the override passcode information, and if valid, authorizes the local security device to override access security.Type: GrantFiled: March 31, 1997Date of Patent: July 13, 1999Assignee: Compaq Computer CorporationInventors: Mark P. Vaughan, Derrill L. Sturgeon
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Patent number: 5919266Abstract: A fault tolerant multiple processor data processing system is described. The system includes a number of processors linked together in a network. One processor is designated the master processor and coordinates the operation of all of the processors. The network is coupled to a number of memory devices which store information which is utilized by the processors. The apparatus includes a redundant mechanism for identifying a failure of a processor. If the master processor fails, a new master processor is selected, in a dynamic manner, from the remaining operative processors. The selection of a new master processor is based upon a contention operation in which the operative processors contend to become the new master processor.Type: GrantFiled: April 2, 1993Date of Patent: July 6, 1999Assignee: Centigram Communications CorporationInventors: Raman K. Sud, Chris Koverman, Jingsong Cai, Thomas Hill
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Patent number: 5919267Abstract: A fault diagnostics system for monitoring the operating condition of a host system, e.g., an aircraft, which includes a plurality of subsystems. The fault diagnostics system is preferably implemented in software running on a high-speed neural network processor. The fault diagnostics system constructs a neural network model of the performance of each subsystem in a normal operating mode and each of a plurality of different possible failure modes. The system preferably dynamically predicts the performance of each subsystem based upon the response of each of the neural network models to dynamically changing operating conditions, compares the actual performance of each subsystem with the dynamically predicted performance thereof in each of the normal and possible failure modes, and determines the operating condition of the host system on the basis of these comparisons.Type: GrantFiled: April 9, 1997Date of Patent: July 6, 1999Assignee: McDonnell Douglas CorporationInventors: James M. Urnes, William E. Bond
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Patent number: 5916314Abstract: In a digital computer with a cache comprised of N sets labeled 0 to N-1, cache tag memory for each set is divided into primary and mirror parts, each part with sufficient capacity to store a number of cache tags equal to the number of cache blocks storable in a cache memory associated with each set. Every modification or installation of cache tags in the primary part of a set x is accompanied or followed by identical modification or installation of cache tags in the mirror part of a set F(x), where F is a one-to-one function that maps the set of integers from 0 to N-1 onto itself. Cache tag lookup retrieves a first set of N cache tags from the primary part of each cache tag memory, and parity checking is performed on each tag. If a parity error is found, a set of cache tags is retrieved from the mirror part of the cache tag memories, and parity checking is again performed. If no error is found, cache processing proceeds normally.Type: GrantFiled: September 11, 1996Date of Patent: June 29, 1999Assignee: Sequent Computer Systems, Inc.Inventors: Thomas B. Berg, Tapas Datta
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Patent number: 5913024Abstract: A secure commerce server system and method. A secure commerce server system includes a plurality of regions or burbs, including an internal burb and an external burb, a commerce server and an administration server. Processes and data objects associated with the administration server are bound to the internal burb. Processes and data objects associated with the commerce server are bound to the external burb. Processes bound to one burb cannot communicate directly to processes and data objects bound to other burbs. The administration server cannot be manipulated by a process bound to the external burb.Type: GrantFiled: February 9, 1996Date of Patent: June 15, 1999Assignee: Secure Computing CorporationInventors: Michael W. Green, Andrew W. Jensen
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Patent number: 5903721Abstract: A method for executing a secure online transaction between a vendor computer and a user computer, wherein the vendor computer and the user computer are interconnected to a computer network such as the Internet for data communications therebetween.Type: GrantFiled: March 13, 1997Date of Patent: May 11, 1999Assignee: cha|Technologies Services, Inc.Inventor: Timothy Sixtus
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Patent number: 5901153Abstract: A dynamic random access memory (DRAM) classification method is disclosed, including a test/classification apparatus controlled by a test/classification control process. The test/classification apparatus includes a programmable logic control (PLC), test devices, a conveyor device, electromagnetic driver devices, a man-machine interface, sensors and an alarm. The PLC is operated in accordance with the test/classification control process to control the test devices for performing test on DRAMs supplied from at least two supply rails. The electromagnetic driver devices are then used to move the DRAMs so tested to the conveyor device which in turn conveys the DRAMs to a particular collection position in accordance with the characteristic value obtained in the test, which characteristic value being within a particular class of DRAM associated with such a particular collection position, to achieve conveyance and classification of the DRAM.Type: GrantFiled: September 10, 1997Date of Patent: May 4, 1999Assignee: Behavior Tech Computer Corp.Inventor: Ching-Tsan Chuang
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Patent number: 5901279Abstract: A method of coupling logic devices using spares. A first logic device is coupled to a second logic device using a first plurality of spares. The first logic device is coupled to a third logic device using a second plurality of spares. The second logic device is coupled programmatically to the third logic device by coupling programmatically one of the first plurality of spares to one of the second plurality of spares via the first logic device. The coupling of the first logic device to the second logic device and the coupling of the first logic device to the third logic device comprise coupling a total number of spares not exceeding M(N-1), wherein M is a minimum number of spares that must be coupleable between each potential pair of logic devices in a multiplicity of logic devices, and wherein N is a total number of logic devices in the multiplicity of logic devices.Type: GrantFiled: October 18, 1996Date of Patent: May 4, 1999Assignee: Hughes Electronics CorporationInventor: Robert W. Davis, III
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Patent number: 5896496Abstract: A polling is executed periodically among each of nodes connected by a transmission path mutually. The node recognizes that a defect occurred in a connection state of the transmission path, when it detects a lack of a periodic polling from an adjacent node three times. Then, the node registers that all of permanent connections which are set up so as to pass through the transmission path are invalid in its Permanent Virtual Circuit (PVC) management table, and notifies the invalidity of the permanent connection to the node of the next step in the permanent connection. The node of the next step which received the notification registers that the notified permanent connection is invalid in its PVC table and notifies the invalidity of the notified permanent connection to the node of the further next step.Type: GrantFiled: June 10, 1997Date of Patent: April 20, 1999Assignee: Fujitsu LimitedInventor: Yuko Suzuki
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Patent number: 5894552Abstract: A secured network system comprising a readykey controller connected to a st card reader and a power relay switch. The user inserts a microchip embedded card into the first card reader which transmits a first electrical authorization signal to the readykey controller indicating that the user is authorized to use a computer for receiving and processing classified data. The readykey controller then supplies a first enable signal to a power relay switch activating the power relay switch which couples the computer's power supply to an external power source. The secured network system also allows the user to receive and process classified data, by setting a manual A/B switch to a predetermined position which allows a secured network server to be connected to the computer. The user next inserts his proximity card into a second card reader which then transmits a second electrical authorization signal to the readykey controller indicating that the user is authorized to receive and process classified data.Type: GrantFiled: August 15, 1997Date of Patent: April 13, 1999Assignee: The United States of America as represented by the Secretary of the NavyInventors: Stephen W. Bouthillier, Ross E. Seybold, Sydney R. Blowers, Robert V. Sulkowski, Jr., Randall P. Morse
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Patent number: 5889935Abstract: Two data storage systems are interconnected by a data link for remote mirroring of data. Each volume of data is configured as local, primary in a remotely mirrored volume pair, or secondary in a remotely mirrored volume pair. Normally, a host computer directly accesses either a local or a primary volume, and data written to a primary volume is automatically sent over the link to a corresponding secondary volume. Each remotely mirrored volume pair can operate in a selected synchronization mode including synchronous, semi-synchronous, adaptive copy remote--write pending, and adaptive copy--disk. Each write request transmitted over the link between the data storage systems includes not only the data for at least one track in the secondary volume to be updated but also the current "invalid track" count for the secondary volume as computed by the data storage system containing the corresponding primary volume.Type: GrantFiled: March 17, 1997Date of Patent: March 30, 1999Assignee: EMC CorporationInventors: Yuval Ofek, Natan Vishlitzky, Haim Kopylovitz
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Patent number: 5848237Abstract: A programmable digital filter. The digital filter detects a predefined pattern over a programmably variable duration. The filter includes an interval register which is coupled to receive an interval count. A sample register is coupled to receive a plurality of samples of an input signal which is sampled at an interval determined by the interval count. A plurality of pattern matching circuits generate a pattern match output if the plurality of samples matches one of a plurality of predetermined patterns, and a state logic circuit generates a signal if a new match is found. The pattern matching circuits may be stable high and stable low test circuits which cooperate to determine if all of the plurality of samples are of a consistent logic value.Type: GrantFiled: May 15, 1996Date of Patent: December 8, 1998Assignee: Intel CorporationInventors: Leonard Cross, David W. Bogardus
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Patent number: 5802271Abstract: A terminal device management system includes a plurality of terminal devices and a remote management apparatus for remotely managing the plurality of terminal devices. The remote management apparatus includes a data receiving section, a management table storing section for storing a management table including identifiers for the terminal devices which are set to transmit data in a transmission time interval for identifying whether data has been Bent from the terminal devices or not, a timer section for measuring a time period during which a line is not connected in the transmission time interval, and a control section for detecting whether or not the time period measured by the timer section reaches a predetermined time period, and for, when it is detected that the predetermined time period is reached, detecting a terminal device the identifier of which in the management table stored in the management table storing section indicates data has not been received therefrom, as a failed terminal device.Type: GrantFiled: October 15, 1993Date of Patent: September 1, 1998Assignee: Mita Industrial Co., Ltd.Inventors: Yasuhiro Hashimoto, Masahiro Sako, Hiroyuki Inenaka, Yuji Yamashita