Abstract: System (10) comprising at least two units (1, 2) with clock functionality, the units being coupled to a common system clock line (SCLK), a common internal clock line (ICLK), and a logic bus (L-BUS), whereby one sole unit (1, 2) is being dedicated as a mater unit at a time. One source clock signal (CLK10, CLK20) of a unit is output on the internal clock line (ICLK) and all PLL devices of all units generates PLL output signals derived from the internal clock signal, the outputs of the PLL devices (CLKP1, CLKP2) being in phase with one another such that switchover from one PLL output signal to another is seamless.

Abstract: A bus data signal is applied to a tapped data delay line. The various increasingly delayed data values present at the taps of the delay line are clocked into respective cells of a sticky ZEROs register (SZERO) previously initialized to all ONES, and into respective cells of a sticky ONES (SONE) register previously initialized to all ZEROS. SZERO measures the unit interval of a ONE.

Abstract: A method is presented for estimating a phase error for first (rI) and second (rQ) orthogonal signal components spread respectively by different first cI and second cQ spreading codes. A cross-despread value IdQ and/or QdI is determined by despreading one signal component with the spreading codes associated with the other signal component (rI with cQ or rQ with cI). In parallel, the same signal component is also despread with its associated spreading code to determine an estimated data symbol for that component. An interference of Q into I or I into Q is calculated and multiplied by the estimated data symbol, and subtracted from the cross-despread value to achieve an estimate of phase error. Preferably, both cross-despread values are obtained, normalized to a common data rate, scaled to maximize signal to noise ratio, and combined into one phase error estimate. A phase error detector includes despreaders, multipliers, and adders to determine the cross-despread value and subtract the interference from it.

Abstract: A modem system for receiving and transmitting signals having a frequency domain equalizer (FEQ) block being responsive to a frequency channel response for processing the same to generate one or more initial FEQ coefficients (FEQ1), the modem system is responsive to an input signal for processing the same to generate frequency channel response, the input signal being generated from a transmitted signal, FEQ block using FEQ1 to generate an equalized Signal, modem system demodulating equalized Signal to generate a demodulated Signal symbol, in accordance with an embodiment of the present invention.

Abstract: The present invention comprises systems, methods, and devices for detecting the presence of a specified signal type by autocorrelating the signal with a time-delayed copy of itself, by simultaneously crosscorrelating the signal with an expected signal type, and by then comparing the results of the autocorrelation and crosscorrelation to determine whether or not the signal is present and to ascertain its type.

Abstract: Phase and amplitude offsets of a multicarrier transceiver may be reduced by measuring receiver amplitude and phase mismatches of receiver radio-frequency (RF) circuitry by performing a fast Fourier transform (FFT) on a receiver calibration signal.

Abstract: A digital detector processes at least one received digital signal to generate a squared signal, encodes the squared signal, applies first and second portions of the encoded signal to a multiplier and a look-up element, respectively, and processes outputs of the multiplier and look-up element to generate a detector output signal representative of a power level of the received digital signal. In an illustrative embodiment, the digital detector is configured so as to exhibit a waveform dependence substantially the same as that of an analog logarithmic amplifier detector. The digital detector and analog logarithmic amplifier detector are utilizable in a closed-loop gain control arrangement for providing a desired gain for a signal path of a base station transmitter in a wireless communication system.

Abstract: A modem system for receiving and transmitting signals having a frequency domain equalizer (FEQ) block being responsive to a frequency channel response for processing the same to generate one or more equalizer coefficients, the modem system is responsive to an input signal for processing the same to generate frequency channel response, the input signal being generated from transmission of a transmitted signal, FEQ block for using equalizer coefficients to generate an equalized channel response, modem system for using equalized channel response to generate one or more metric weights, in accordance with an embodiment of the present invention.

Abstract: Disclosed is a chip-level or a symbol-level equalizer structure for a multiple transmit and receiver antenna architecture system that is suitable for use on the WCDMA downlink. The equalizer structure takes into account the difference in the natures of inter-antenna interference and multiple access interference and suppresses both inter-antenna interference and multiple access interference (MAI). Enhanced receiver performance is achieved with a reasonable implementation complexity. The use of the CDMA receiver architecture, in accordance with this invention, enables the realization of increased data rates for the end user. The CDMA receiver architecture can also be applied in conjunction with space-time transmit diversity (STTD) system architectures.

Abstract: A technique for peak suppression, phase and amplitude equalizer of multi-carrier signals with different modulation is described. The input to the multi-carrier power amplifier is modified by a peak suppression, phase and amplitude equalizer circuit prior to being applied to the amplifier. The peak suppression is applied to a multi-carrier signal with different modulations and bandwidth. After peak suppression each individual carrier is phase and amplitude equalized to maintain the properties of the multi-carrier signal. The phase equalizer maintain the timing property of the carriers and the amplitude equalizer maintain the modulation accuracy of the individual carriers. The input to the peak-to-average reduction circuit could be a baseband, an intermediate frequency (IF) or radio frequency (RF) signal. The peak-to-average reduction is performed in digital domain.

Abstract: A novel technique and structure that maximizes the extraction of information from reference pulses for UWB-TR receivers is introduced. The scheme efficiently processes an incoming signal to suppress different types of UWB as well as non-UWB interference prior to signal detection. Such a method and system adds a feedback loop mechanism to enhance the signal-to-noise ratio of reference pulses in a conventional TR receiver. Moreover, sampling the second order statistical function such as, for example, the autocorrelation function (ACF) of the received signal and matching it to the ACF samples of the original pulses for each transmitted bit provides a more robust UWB communications method and system in the presence of channel distortions.

Abstract: Method and apparatus for providing an amplified modulated radio frequency signal, the method comprising the steps of providing a radio frequency (RF) oscillatory signal, generating from the RF oscillatory signal and an input signal a pair of phase modulated phase conjugated signals, and summing the pair of signals to provide the desired modulated RF signal output. A form of the invention is applied to digital modulation using in-phase (I) and quadrature (Q) input signals. Each of the I and Q signals is processed in a respective channel, with the channel outputs being summed. The channels share an RF oscillatory signal, which is phase shifted by 90 degrees within the Q channel.

Abstract: A method and apparatus for compensating I/Q imbalance in receivers is described. The method includes determining a difference between energies of two quadratures, correcting an amplitude imbalance using the difference between the energies of two quadratures, determining a cross-correlation between the two quadratures, and correcting a phase imbalance using the cross-correlation between the two quadratures.

Abstract: A carrier recovery apparatus capable of detecting a phase error of modulation signal by a simple calculation, reducing the circuit scale, and improving the frequency capture characteristic and phase jitter characteristic is presented. This carrier recovery apparatus comprises a symbol estimating unit for estimating the transmitted symbol, a phase error detector for generating a normalized phase error signal on the basis of the estimated symbol and reception signal, a loop filter for filtering the phase error, and a numerical control oscillator controlled by the loop filter.

Abstract: A method for processing an input burst signal comprising a first step for identifying an additive DC component and generating an output signal, which is representative for an estimated value of said DC component. The method further comprises a second step for detecting a predetermined signal portion from a plurality of possible signal portions included in the input burst signal and generating a control signal indicating the presence of the predetermined signal portion in the input burst signal. The method is characterized in that the first step and the second step are performed in parallel i.e. in a commonly defined time interval from a starting time of the burst.

Abstract: A transmitting method and a transmitter apparatus, which need no manual adjustment, are disclosed. A delay amount is automatically adjusted such that an out-of-band distortion component of a transmission signal is minimized, and a correct timing is produced by the method and the apparatus. In this transmitter apparatus, a first delay adjusts a control timing over a voltage that controls a power amplifier, and a distributor distributes an output from the power amplifier in order to feedback parts of the output. A distortion adjusting units calculating a distortion component of the transmission signal by using the signal fed back by the distributor, and adjusts automatically a delay amount of the first delay so as to minimize the distortion component. This structure allows eliminating manual adjustment, and obtaining high power-efficiency with fewer distortions.

Abstract: A coefficient computing section, for computing a characteristic reverse to an input/output characteristic of the power amplifier, is configured by a fixed coefficient storing section and an error coefficient computing section. The fixed coefficient storing section is previously stored with the characteristic reverse to a pre-measured input/output characteristic. The error coefficient computing section computes an error coefficient between a characteristic stored in the fixed coefficient storing section and a current characteristic of the power amplifier. When the determining section determines that the adjacent-channel leak current power ratio is greater than a predetermined value, an operation halt is instructed to the power amplifier.