Abstract: A split-gate flash memory structure. The flash memory at least includes a substrate having a trench therein, a floating gate, a select gate and a source/drain region. The floating gate is formed inside the trench such that the upper surface of the floating gate is below the substrate surface. The select gate is also formed inside the trench above the floating gate such that the select gate protrudes beyond the substrate surface. The source/drain region is formed in the substrate on each side of the select gate. The source/drain region and the floating gate are separated from each other by a distance. A tunnel oxide layer separates the floating gate from the substrate and a gate dielectric layer separates the floating gate from the select gate. A dielectric layer separates the select gate from the substrate.

Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 .ANG.. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted into regions of the active areas in close proximity to the trench isolation structure.

Abstract: Method of fabricating a junction field effect transistor employing self-alignment techniques. The active regions of the device are defined by a relatively thin thermally-grown isolating silicon oxide layer at the surface of a silicon body. After the active source and gate regions of the device as defined by the thermally-grown isolatign silicon oxide are formed in the silicon, a layer of deposited silicon oxide is formed over the thermally-grown silicon oxide. This method provides a thick dielectric layer as well as control of the horizontal dimensions of the source and gate contacts.

Abstract: A fuel cell system has a core in the form of a support having cavities passing therethrough and surfaces on which a multiplicity of fuel cells are disposed and mutually interconnected in series and in parallel by conductor tracks. The support is produced by an extrusion process. The conductor tracks and insulating layers are applied to the surfaces by screen printing and are permanently joined to the support by sintering. The fuel cells are assembled from individual layers and produced by a sheet casting and a screen printing process and are joined permanently to the support by adhesive sintering.

Abstract: A method of making bonding bumps on the pads of an electrical chip including depositing a layer of metallic adhesion material over the surface, depositing metallic bumps on the metallic adhesion material over each of the pad areas using a focused liquid metal ion source, and chemically etching the layer of metallic adhesion material off the surface outside of the deposited bumps.

Abstract: A method of manufacturing a photovoltaic device, wherein an amorphous semiconductor layer of one conductivity type doped with impurities which determine the conductivity type is formed on a substrate having a conductive surface, an insulating film is formed on this amorphous semiconductor layer, the insulating film is patterned to partially form aperture regions where the surface of said amorphous semiconductor layer is exposed, an intrinsic amorphous semiconductor layer on said insulating film and the aperture regions formed over the substrate, the amorphous semiconductor layer of one conductivity type and the intrinsic amorphous semiconductor layer are thermally treated, crystallization is advanced using the amorphous semiconductor layer of one conductivity type located beneath said aperture region as a core to form a polycrystal semiconductor layer of one conductivity type, a semiconductor layer of the other conductivity type is formed on this polycrystal semiconductor layer, and an electrode is formed in

Abstract: According to the structure of the invention, an AlGaInP cladding layer of one conductive type, an active layer, and an AlGaInP cladding layer of other conductive type greater in thickness in stripes are formed on a GaAs substrate, and an insulating film, AlGaInP or amorphous layer smaller in refractive index than the AlGaInP cladding layer are formed at both sides of the stripes, wherein the light can be confined and guided also in the direction parallel to the active layer, and the light can be index-guided both in the direction parallel to the active layer and in the direction vertical thereto, so that a laser having an extremely smaller astigmatism may be presented. What is more, the current blocking layer disposed at the outer side of the insulating film, AlGaInP or amorphous layer is high in thermal conductivity, and the heat generated in the vicinity of the active layer may be efficiently released.The invention also relates to the method of fabricating the laser composed in such structure.

Abstract: Group VIB metal sulfide slurry catalysts having a pore volume in the pore size range 10 to 300.ANG. radius of at least 0.1 cc/g. Also, Group VIB metal sulfide catalysts having a surface area of at least 20 m.sup.2 /g. Suitable Group VIB metals are molybdenum and tungsten, preferably molybdenum. The Group VIB metal sulfide can be approximately a Group VIB metal disulfide. The slurry catalyst can be promoted with a Group VIII metal, such as nickel or cobalt.