Abstract: A digital finite impulse response (FIR) filter is provided in which a plurality of weighted signal taps are symmetrically located in time about a weighted center tap. Weighted signals from the symmetrically located taps are summed at a first point in the filter, which sum is then combined with signals from the center tap in one sense, that is, either additively or subtractively, to produce signals at a first output. The summed signals at the first point are also combined with signals from the center tap in an opposite sense to produce signals at a second output. The two outputs will exhibit bandpass and lowpass filter response characteristics, with the outputs at which the respective responses are produced being determined by the respective senses of signal combination. The FIR filter may be of either the input tap-weighted or output tap-weighted variety.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data; however, the accumulator in the data path may be used as a program address source for table-read and table-write, for example. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances, such as accumulator addressing. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract: The invention relates to a method for preventing at a vehicle gearbox selection of an operationally erroneous gear in the absence of a gear change regulating speed signal. The absence of the gear change regulating signal is detected by a fault detection circuit or by a fault detection routine, which thereby sends an output signal to an operative circuit or the like. The operative circuit ensures that erroneous gear selection is prevented and/or triggers a fault indication.With the intention of ensuring that a fault already existing when the vehicle starts can be detected, the invention is essentially distinguished in that during the fault detection routine it is determined whether the engine is running, whether a forward gear is engaged, the clutch is engaged, and whether and with these conditions extant whether the speed has attained a given minimum speed within a predetermined time.

Abstract: A simple method and apparatus for generating approximate sine waves is described. A digital accumulator or adder is driven at a basic counting rate to accumulate increments representative of phase with the total sum representative of total phase angle of a sine wave. The output is periodically sampled and the value is converted into an analog output voltage in a normal D to A converter. A straight line ramp voltage approximation to the sine wave function is created as the result. The accumulator operates in this fashion until a total phase angle of approximately 45.degree. is accumulated. Then accumulation value additions are then accorded 1/2 their usual significance until 671/2.degree. of total phase angle are accumulated. Then accumulation is then at 1/4 the basic significance accorded to increments until 90.degree. is reached. The symmetry of the sine wave allows the 0.degree. through 90.degree. samples to be used to generate the full 360.degree.

Abstract: An improved controller for a VTR is disclosed. The VTR has a time code reader and a tape time reader, each generating a signal representative of the time length of the material recorded on the tape. The time code reader generates a signal derived from the time code recorded on the tape. The tape time reader generates a signal derived from the signals generated by a tachometer, connected to the tape transport mechanism. An interpolated time code is generated by means which adds an offset value to this tachometer derived time data. The offset value is periodically calculated by means which determines the difference between the time code data and the tachometer time code data after first determining that the tape speed has exceeded a predetermined threshold speed for a predetermined period of time. If the tape speed has not exceeded this predetermined threshold speed, then the last calculated offset is added to the tachometer derived data.

Abstract: An interface (10) between a first (MC, 30) and second (SC) computer employs a multiplexer (46) and a coupler (48, 50). The first (MC, 30) and second (SC) computers have a first (LA/B, LEX0-15) and second (CX1-21, CA1-15) plurality of information lines, respectively. These computers also each have a group of control lines (36, 42). The multiplexer (46) is connected to the first and second plurality of information lines (LA/B, LEX0-15, CX1-21, CA1-15). The multiplexer (46) is operable to separately switch each of a predetermined group (LEX12-15) within the first plurality (LA/B, LEX0-15) between either member of a different corresponding pair within the second plurality (CX1-21, CA1-15). The multiplexer (46) is also connected to at least one (ESELCX) of the control lines (36) of the first computer (MC, 30). The multiplexer (46) can switch the predetermined group (LEX12-15) in response to a signal on the control lines (ESELCX) of the first computer (MC, 30).

Abstract: The invention relates to a method for preventing, in a vehicle transmission coacting with a system for automatic gear selection, the selection of an operationally incorrect gear in the case where a signal representing a vehicle wheel rotational speed, e.g. during braking of the vehicle, does not constitute a correct representation of the vehicle speed. There is thus calculated in the system the wheel rotational speed change, which is compared with a predetermined retardation value. If the retardation limiting value is exceeded, an operative circuit or the like is activated for ensuring that an incorrect gear selection is prevented, e.g. by selecting neutral gear.

Abstract: A data processing system includes a number of subsystems, all coupled in common to a system bus. Also coupled to the system bus is a hardware monitor interface unit (HMIU) for receiving all information transferred between subsystems. The HMIU includes programmable hit matrices (PHM's). The PHM's include memory circuits which generate "hit" signals when predetermined information addresses the memory circuits. The "hit" signals or binary ONE's are loaded into the memory circuits during a load mode during which system bus information specifically addressing the HMIU is received on two system bus cycles for each address location of the memory circuit. The data bus contains the memory circuit address during the first system bus cycle and the data during the second data bus cycle. An address bus signal identifies the cycle.

Abstract: In combination with a host processor CPU, means are provided to a standard computer terminal keyboard to reconfigure an identity change of the keyboard for another use/uses and to identify its new configuration, status and other vital information to the host CPU.

Abstract: The device performs the function ##EQU1## for image processing, where W.sub.i are fixed weights for any specific application. It uses a PROM and accumulator algorithm, in which the memory stores the values ##EQU2## in 2.sup.M words, with addresses formed from one bit of each data word in a given bit position. In operation the most significant bit of each data word is used first to address memory, and in successive clock cycles the other bit positions are used down to the least significant. The memory output words are supplied to the adder-accumulator, and in each clock cycle the adder-accumulator output is shifted left one bit and used as a second input thereof. Then if the data words have N bits designated j=0 to N-1, after N clock cycles the memory output words have each been effectively multiplied by 2.sup.j and accumulated in the sum.