Abstract: Disclosed are methods and apparatuses for combined etching and cleaning of semiconductor wafers and the like preferably using hydrofluoric acid (HF), hydrochloric acid (HCl) and water solutions which generate equilibrium vapor mixtures of HF vapor, HCl vapor and water vapor as a homogenous processing gas. The processing gases do not employ a carrier gas which will make the vapors nonhomogeneous and reduce etching rates. The vapors are preferably generated from a liquid source which is provided within a contained reaction chamber which holds the wafer. The wafer is preferably oriented with the surface being processed directed downward. The wafer is advantageously positioned above or in close proximity to the liquid source of the processing vapor.

Abstract: A method for manufacturing a semiconductor device including a combined stack-trench type capacitor is disclosed. The method comprises the steps of: forming a conductive layer serving as a first electrode of the capacitor both on the inside region of a trench and on a transistor and forming a planarizing layer on the conductive layer; forming a photoresist pattern on the planarizing layer; etching the planarizing layer and the conductive layer; and removing the planarizing layer. The sandwiched planarizing layer between the second conductive layer and the photoresist pattern prevents the exposing of the first electrode pattern during the photoetching, so that uncontaminated uniform dielectric film can be obtained.

Abstract: Disclosed are methods and apparatuses for combined etching and cleaning of semiconductor wafers and the like using a combined etchant and cleaning agent, particularly hydrofluoric acid (HF) and hydrochloric acid in water mixtures. Homogeneous vapor mixtures are generated from homogeneous liquid phase mixtures which are preferably recirculated, mixed and agitated. The liquid phase is advantageously circulated through a chemical chamber within the processing bowl. Exposure of wafers to vapors from the chemical chamber can be controlled by a vapor control valve which is advantageously the bottom of the processing chamber. The wafer is rotated or otherwise moved within the processing chamber to provide uniform dispersion of the homogeneous reactant vapors across the wafer surface and to facilitate vapor circulation to the processed surface. A radiative volatilization processor can be utilized to volatilize reaction by-products which form under some conditions.

Abstract: A method of producing a semiconductor device which comprises; a first cleaning step of cleaning the surface of Si of a semiconductor device having an Si base or an Si thin film as a substrate (1) by using an APM solution; a second cleaning step of cleaning the surface of Si by using a dilute HF solution to thereby remove the uppermost surface layer (3) of a naturally oxidized film (2) formed in the first cleaning step; and a step of forming a silicon oxide film by thermally oxidizing the cleaned surface of the naturally oxidized film (2).

Abstract: A long-life, electrically writable and erasable non-volatile semiconductor memory device is disclosed. The memory device is fabricated in the following steps. After forming a first gate insulating film on a semiconductor substrate, a window is opened in the first gate insulating film to expose a portion of the surface of the semiconductor substrate, using a two-step etching technique in which dry etching and wet etching are performed successively. The exposed portion of the semiconductor substrate not over-etched is selectively oxidized to form a tunnel insulating film (second gate insulating film) having edge portions resistant to dielectric breakdown. Thereafter, a floating gate, a third gate insulating film, and a control gate are formed sequentially. The floating gate is patterned in such a way as to cover the entire tunnel insulating film or cross only a portion of an edge of the tunnel insulating film.

Abstract: A structure is formed from two layers of material having opposite conductivity types. A first region is formed within the structure, and extends at least in part into a layer to be etched. A surface of the structure is then masked and etched. The result is a microstructure which varies with the conductivity type and geometry of the region formed and etchant used.

Abstract: An ion implanting method which suppresses defects by changing the shape of the amorphous layer formed by ion injection from that of a conventional device.After forming a mask pattern on a semiconductor wafer, amorphous layers are then formed with sufficient penetration under the mask material by implanting ions at an implant angle greater than or equal to 20 degrees with a dose amount enough for forming amorphous layers. In this large angle ion implanting method, the edge of each amorphous layer becomes dull and, thereby, no voids are formed in a successive heat treatment.

Abstract: The method of making a pressure sensor formed of semiconductor material on an insulating support, i.e., as a semiconductor-on-silicon, is described. The sensor is comprised of four piezoresistive gauges formed in the semiconductor material. Two of the gauges, each have a pair of limbs joined by a base, such that they are U-shaped, and two others are I-shaped. Each of the four gauges comprise two half-gauges, and each half-gauge comprises an elongated sensing zone in semiconductor material and having a reduced width in the plane of the insulating support. Two ohmic contact zones are disposed at the ends of each of the half-gauges, and two connection zones in semiconductor material and of greater width are disposed between the sensing zones and the ohmic contact zones, the form of the two connection zones are the same for each of the eight half-gauges.

Abstract: An embodiment of the present invention is a method for determining the cleanliness of a semiconductor wafer initially deposited with polysilicon, patterned with photoresist, processed, and then having the resist removed under standard conditions. The method comprising the steps of: depositing a thin TEOS film over the entire surface of a wafer; exposing said wafer to a solution of hot potassium hydroxide (KOH) that attacks polysilicon and is highly selective to and does not etch said TEOS film, the exposing such that if any pin hole exists in the TEOS film an underlying layer of polysilicon is attacked vigorously; and inspecting said wafer for a visual indication in said polysilicon layer of whether or not said polysilicon layer was attacked by the exposure to said potassium hydroxide (KOH).

Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO.sub.2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

Abstract: Silicon wafers are first subjected to an oxidative treatment and subsequey to exposure to organosilicon compounds which contain at least one radical in the molecule which is hydrolyzably bound to the silicon and at least one radical in the molecule having hydrophilic properties. Depending on the compound selected, more or less strongly hydrophilic or hydrophobic properties of the silicon surface can consequently be established under mild conditions. The wafers treated in such a manner have a high storage stability and retain their surface nature even under difficult climatic circumstances. The surface nature present after the oxidative treatment can then be restored particularly easily by hydrolysis.

Abstract: A method for fabricating a semiconductor device comprises the steps of providing an oxide film containing silicon and oxygen on a substrate, introducing species containing oxygen into the oxide film by an ion implantation process, and providing an electrode on the oxide film.

Abstract: In an apparatus and a method for cleaning semiconductor wafers, an exhaust chamber having a sub-outlet slows down the flow of frozen micro-particles and thus prevents rebounding of the particles toward the wafer. Therefore, dust or the like is kept away from a cleaned semiconductor wafer so that the semiconductor wafers are cleaned more thoroughly.

Abstract: Disclosed is a method of forming an interconnection pattern which causes no disconnection even when making contact with water in the atmosphere. An interconnection layer is formed on a semiconductor substrate. The interconnection layer is selectively etched by employing a halogen-type gas, to form an interconnection pattern. Ultraviolet rays are directed onto the interconnection pattern in the atmosphere including a hydrogen gas. This method avoids generation of hydrogen halogenide which causes corrosion of metal interconnections even when the metal interconnections make contact with water in the atmosphere, thereby to prevent disconnections of the metal interconnections.

Abstract: Adjacent buried contacts (11, 12, 13) formed at the principal surface of a well or substrate region (14) of a semiconductor device, each having a doped contact region (29, 30 31) of one conductivity type and a punch-through prevention region (36, 37, 38) of the opposite conductivity type surrounding the lower portion of the doped contact region are provided. The punch-through prevention region may advantageously be of the same conductivity type as the substrate. By performing an extra implant or other impurity introduction step while the mask to etch the contacts through the dielectric layer remains in place, the procedure to provide punch-through protected buried contacts may be easily integrated into current processes without the need for an extra mask. Such a structure and procedure enables buried contacts to be spaced closely together without over-doping the well region (14) in which source-drain regions (40, 42, 44, 46) are also formed thus avoiding a degradation in device performance.

Abstract: A high-purity II-VI semiconducting compound can be produced by initially preparing a substrate of a II-VI semiconducting compound by a chemical transport method with a halogen as transport medium and then epitaxially growing a layer of a II-VI compound on this substrate.

Abstract: A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.

Abstract: A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body.The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

Abstract: Disclosed is a method which enables a sufficient anti-corrosion processing of an interconnection pattern. An interconnection layer is formed on a semiconductor substrate. The interconnection layer is selectively etched by employing a halogen-type gas, so as to form an interconnection pattern. The interconnection pattern is irradiated with deep UV light in a vacuum of 1.times.10.sup.-4 Torr or less in degree. Even if a protection film including halogen is formed on the side wall of the interconnection pattern upon reactive ion etching, this method enables sufficient removal of the halogen in a sufficient time and a complete anti-corrosion processing of the interconnection pattern.

Abstract: A new-type silicon material is produced by hydrogen ion implantation and subsequent annealing, the annealing being preferably in two steps. The present invention raises surface mobility of a silicon wafer and produces a buried high-resistivity layer beneath a silicon surface layer. The resulting products are particularly useful for the improvement of yield and speed and radiation hardness of very large scale integrated circuits.