Patents Examined by Ourmazo S. Ojan
  • Patent number: 5132247
    Abstract: A quantum effective device and its method of manufacture are disclosed, wherein said device comprises quantum well boxes composes of a semiconductor substrate and a compound semiconductor on the surface of the semiconductor substrate at least comprising a first and a second elemental component and a semiconductor overlayer overlying said quantum well boxes and the surface portion of the exposed semiconductor substrate and wherein the quantum well boxes have an epitaxially grown single crystal structure obtained by depositing fine droplets of liquid phase composed of the first elemental component on the surface of the semiconductor substrate in the heated state and then incorporating a second elemental component different from the first elemental component in said droplets.
    Type: Grant
    Filed: September 28, 1990
    Date of Patent: July 21, 1992
    Assignee: National Research Institute for Metals
    Inventors: Toyohiro Chikyou, Sinya Hashimoto, Satoshi Takahashi, Nobuyuki Koguchi
  • Patent number: 5110750
    Abstract: For compensating a decreased impurity concentration at a peripheral portion of a well region provided in a semiconductor substrate, an impurity whose conductivity type is same as that of the well region is diffused into the peripheral portion thereof to form a diffused region thereon. Therefore, the well region having the approximately uniform surface impurity concentration is provided.
    Type: Grant
    Filed: August 2, 1990
    Date of Patent: May 5, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Munehiro Yoshida
  • Patent number: 5091339
    Abstract: Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias.
    Type: Grant
    Filed: July 23, 1990
    Date of Patent: February 25, 1992
    Assignee: Microelectronics and Computer Technology Corporation
    Inventor: David H. Carey