Patents Examined by Pajnikant B Patel
  • Patent number: 6175218
    Abstract: Disclosed is a Power Factor Correction (PFC) controller which comprises a boost converter, an error amplification unit, a calculator, and a switching driver. The error amplification unit reduces the error voltage of the output voltage of the boost converter to a specific reference voltage. The calculator receives first and second input voltages proportional to the input power of the converter and the output voltage of the error amplification unit, and outputs the voltage proportional to the first input voltage and the output voltage of the error amplification unit and inversely proportional to the second input voltage. The switching driver controls the switch to OFF when the voltage which detects the current flowing to switch of the boost converter becomes equal to the output voltage of the calculator, and controls the switch to ON when the zero current of the coil of the boost converter is detected.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: January 16, 2001
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Nak-Choon Choi, Kyung-Hee Jang, Maeng-Ho Seo
  • Patent number: 5771161
    Abstract: A supplementary DC power source is coupled to the DC link circuit of an active power line conditioner (APLC) for sustaining uninterrupted AC power to a load during the time interval needed for AC power restoration or for an alternate or a back-up AC source to be brought on line to power the load upon temporary or continued failure of an AC power source. The supplementary DC source is comprised of a rectifier circuit across which is connected a storage capacitor. A boost converter and an auctioneer diode are coupled between the storage capacitor and the DC link circuit so that when the DC link drops in voltage in response to a sag in the AC source voltage upon loss of the AC voltage source, the necessary power is provided by the storage capacitor and boost converter. A pair of fast acting switches are also coupled between the AC source and the power bus feeding the inverters to isolate the AC source from the APLC and the load upon loss of the AC source.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: June 23, 1998
    Assignee: Northrop Grumman Corporation
    Inventors: Kenneth R. Jackson, Stephen A. Lane