Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.

Abstract: The present invention provides a semiconductor device, including at least two gate structures, and each gate structure includes a gate, a spacer and a source/drain region, the source/drain region disposed on two sides of the gate. A first dielectric layer is disposed on the substrate and between two gate structures, where the first dielectric layer has a concave surface, and the first dielectric layer directly contacts the spacer. A floating spacer is disposed on the first dielectric layer and on a sidewall of the gate, and at least one contact plug is disposed on the source/drain region, where the contact plug directly contacts the floating spacer.

Abstract: Dummy bit lines of are formed in a sacrificial layer at locations where bit lines are to be formed, with bit lines separated by trenches that extend through the sacrificial layer. Enclosed air gap structures are formed in the trenches between the dummy bit lines. Subsequently, the dummy bit lines are replaced with metal to form bit lines.

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

Abstract: The present invention provides a method of manufacturing a phosphor for a light-emitting diode, including filling a phosphor frame in which phosphor models are formed in an engraving form with a fluorescent material solution including a fluorescent material that converts light provided by the light-emitting diode into white light by changing a wavelength of the light provided by the light-emitting diode, polishing a top surface of the phosphor frame filled with the fluorescent material solution, and drying the phosphor frame filled with the fluorescent material solution and polished.

Abstract: An image sensor including a semiconductor layer; a stack of insulating layers resting on the back side of the semiconductor layer; a conductive layer portion extending along part of the height of the stack and flush with the exposed surface of the stack; laterally-insulated conductive fingers extending through the semiconductor layer from its front side and penetrating into said layer portion; laterally-insulated conductive walls separating pixel areas, these walls extending through the semiconductor layer from its front side and having a lower height than the fingers; and an interconnection structure resting on the front side of the semiconductor layer and including vias in contact with the fingers.

Abstract: A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark trench. An alignment/overlay mark includes at least one insulating material positioned within the alignment/overlay mark trench. The alignment/overlay mark is devoid of any of the fin structures.

Abstract: Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.

Abstract: A method of manufacturing a light emitting element includes, sequentially, (a) forming a mask layer for selective growth; (b) forming a layered structure body by layering a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; (c) forming, on the second surface of the second compound semiconductor layer, a second electrode and a second light reflecting layer formed from a multilayer film; (d) fixing the second light reflecting layer to a support substrate; (e) removing the substrate for manufacturing a light emitting element, and exposing the first surface of the first compound semiconductor layer and the mask layer; and (f) forming a first light reflecting layer formed from a multilayer film and a first electrode on the first surface of the first compound semiconductor layer.

Abstract: A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer.

Abstract: A package structure includes a carrier, an electronic component disposed on the carrier, an encapsulant formed on the carrier for encapsulating the electronic component, a first shielding layer formed on the encapsulant, and a second shielding layer formed on the first shielding layer. The first and second shielding layers are made of different materials. With the multiple shielding layers formed on the encapsulating layer, the electronic component is protected from electromagnetic interferences. The present invention also provides a method for fabricating the package structure.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier layer is disposed over the substrate and between the substrate and the electrically conductive layer. A dielectric layer is disposed over the moisture barrier layer. The dielectric layer has an elastic modulus that is lower than an elastic modulus of the moisture barrier layer.

Abstract: Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor chips stacked over a semiconductor wafer. The semiconductor wafer comprises a plurality of second semiconductor chips that are arranged in matrix of a plurality of rows and columns. Each of the first semiconductor chips is stacked over and electrically connected to a different one of the second semiconductor chips. The method further includes contacting a probe card to at least one of the first semiconductor chips to perform a first test operation on a corresponding one of the second semiconductor chips with an intervention of the at least one of the first semiconductor chips so that a plurality of tested apparatus each comprising a pair of first and second semiconductor chips stacked with each other is derived.

Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing material without using GeH4 in an etch gas mixture of an etch process for a cyclic deposition/etch (CDE) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient. As a result, the etch time is reduced and the throughput is increased.

Abstract: A semiconductor light emitting element includes: a pit formation layer formed on the first semiconductor layer and having a pyramidal pit; and an active layer formed on the pit formation layer and having a flat portion and an embedded portion which is formed so as to embed the pit. The active layer has a multi-quantum well structure having a well layer and a barrier layer laminated alternately in which each well layer and each barrier layer lie one upon another. The flat portion has a flat well portion corresponding to the well layer. The embedded portion has an embedded well portion corresponding to the well layer. The embedded well portion has a ring portion which is formed in an interface with the flat well portion so as to surround the threading dislocation. The ring portion has a band gap smaller than that of the flat well portion.

Abstract: A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a III-V compound semiconductor material that is different from a material forming the fin in the III-V compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension.

Abstract: Provided is a method of forming a silicon film in a groove formed on a surface of an object to be processed, which includes: forming a first silicon layer on the surface of the object to be processed to embed the groove; doping impurities near a surface of the first silicon layer; forming a seed layer on the doped first silicon layer; and forming a second silicon layer containing impurities on the seed layer.

Abstract: A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a first film on a semiconductor substrate including a common source region, forming a second film on the first film, forming a conductive film on the second film, patterning the conductive film and the second film, to form an active pattern, and patterning the first film and the semiconductor substrate using the active pattern as a mask, to form a pillar; and forming a gate electrode on an outer circumference of the pillar.

Abstract: A method of vapor-diffusing impurities into a diffusion region of a target substrate to be processed using a dummy substrate is provided. The method includes loading the target substrate and the dummy substrate in a substrate loading jig, accommodating the substrate loading jig loaded with the target substrate and the dummy substrate in a processing chamber of a processing apparatus, and vapor-diffusing impurities into the diffusion region of the target substrate in the processing chamber having the accommodated substrate loading jig. The vapor-diffused impurities are boron, an outer surface of the dummy substrate includes a material having properties not allowing boron adsorption.

Abstract: A structure includes a substrate having an insulator layer and a plurality of elongated semiconductor fin structures disposed on a surface of the insulator layer. The fin structures are disposed substantially parallel to one another. The structure further includes a plurality of elongated sacrificial gate structures each comprised of silicon nitride. The sacrificial gate structures are disposed substantially parallel to one another and orthogonal to the plurality of fin structures, where a portion of each of a plurality of adjacent fin structures is embedded within one of the sacrificial gate structures leaving other portions exposed between the sacrificial gate structures. The structure further includes a plurality of semiconductor source/drain (S/D) structures disposed over the exposed portions of the fin structures between the sacrificial gate structures. The embodiments eliminate a need to form a conventional spacer on the fin structures. A method to fabricate the structure is also disclosed.