Abstract: Two embodiments of a digital signal processor are described. Each embodiment is configured with an instruction processing pipeline including an execute-write pipeline stage. When an instruction reaches the execute-write pipeline stage, the instruction is executed and the corresponding result is written to the specified destination. Additionally, the execute-write stage maintains a relatively short pipeline. One embodiment described herein employs an instruction set in which the destination of an instruction may be encoded within a subsequent instruction. The number of bits utilized to encode a particular instruction is reduced by the number of bits that would have specified the destination.

Abstract: A system for transferring data between main memory and an input/output device in a computer system, where device driver software stores an address of a circular buffer into the device and then the device automatically transfers data to or from the buffer. The system reduces complexity within the device by always starting the circular buffer on a page boundary, and allowing the circular buffer to be only one page long. Each time the buffer address passes either zero or half the buffer size, the system interrupts the processor to allow the driver software to transfer, to a hard disk or other area of memory, the contents of the half of the buffer that was just processed. The system further reduces complexity by transferring only eight bits of data into each word of the buffer within memory, therefore avoiding the complexity of byte packing.