Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming an airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate. The airgap is created by forming a sacrificial germanium-containing semiconductor material at the bottom of the source/drain regions prior to the epitaxial growth of the source/drain regions from physically exposed sidewalls of each semiconductor channel material nanosheet of a nanosheet material stack. After inner dielectric spacer formation, the sacrificial germanium-containing semiconductor material can be reflown to seal any possible openings to the semiconductor substrate. The source/drain regions are then epitaxially grown and thereafter, the sacrificial germanium-containing semiconductor material is removed from the structure creating the airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate.

Abstract: The present application relates to an encapsulation film, a method of manufacturing the same, an organic electronic device including the same, and a method of manufacturing the organic electronic device using the same. The present application provides an encapsulation film which can be formed to have a structure in which moisture or oxygen flowing from the outside into an organic electronic device can be effectively blocked, has excellent handling properties and processability, and also has excellent bonding properties with an organic electronic element and durability.

Abstract: Superconducting switch having a persistent and a non-persistent state and its use as a driver in a memory system are described. An example superconducting switch includes a first superconducting layer and a second superconducting layer. The superconducting switch includes a first magnetic layer having a fixed magnetization state. The superconducting switch includes a second magnetic layer capable of being at least in a first or a second magnetization state. The superconducting switch is capable of being in a first state or a second state, and the superconducting switch is configured such that an application of a magnetic field to the second magnetic layer changes a magnetization of the second magnetic layer from the first magnetization state to the second magnetization state placing the superconducting switch in the second state and a removal of the magnetic field automatically returns the superconducting switch from the second state to the first state.

Abstract: An organic light-emitting diode display panel, a method for fabricating the same and a display device are provided. The display panel is divided into a visible area and a non-display area, and includes: a base substrate, a plurality of organic light-emitting diode elements on the base substrate, an encapsulation layer on sides of the organic light-emitting diode elements away from the base substrate, a touch electrode layer on the side of the encapsulation layer away from the organic light-emitting diode elements, a peripheral circuit on the touch electrode layer away from the encapsulation layer, a circular polarizer on the sides of the touch electrode layer and the peripheral circuit away from the encapsulation layer, and an adhesive layer between the touch electrode layer and the circular polarizer.

Abstract: An organic light-emitting diode includes a first electrode and a second electrode that face each other, an organic emission layer between the first electrode and the second electrode, and an inorganic hole injection layer between the first electrode and the organic emission layer. The inorganic hole injection layer includes oxide of a form A-B-O, including an element A and an element B. The element A is one of molybdenum (Mo) and tungsten (W). The element B is one of vanadium (V), niobium (Nb), and tantalum (Ta). An atom content (x) of the element B is greater than 0 and no more than 15 at % (0<x?15 at %) based on a total atom content of the inorganic hole injection layer.

Abstract: A semiconductor light emitting device includes: a light emitting part for emitting ultraviolet light; and a coating part that coats an extraction surface from which the ultraviolet light emitted by the light emitting part is extracted. The coating part includes a resin matrix having a refractive index lower than a refractive index of an inorganic material forming the extraction surface and a hollow part that lowers a refractive index of the coating part as a whole by being dispersed in the resin matrix. The hollow part has an average particle diameter smaller than a peak wavelength of the ultraviolet light emitted by the light emitting part.

Abstract: A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. A second voltage line, and third and fourth voltage lines may be electrically coupled to a first conductivity region and a second conductivity region respectively. Resistive units may be arranged between the third and fourth voltage lines and the second conductivity region. In use, changes in voltages applied between the second and third voltage lines, and between the second and fourth voltage lines may cause resistances of first and second resistive units to switch between lower and higher resistance values. The lower resistance value of the first resistive unit may be different from the lower resistance value of the second resistive unit and/or the higher resistance value of the first resistive unit may be different from the higher resistance value of the second resistive unit.

Abstract: An electronic device, such as, without limitation, a perovskite solar cell or a light emitting diode, includes an assembly including at least one electronic portion or component, and a composite coating layer covering at least part of the assembly including the at least one electronic portion or component. The composite coating layer includes a polymer material, such as, without limitation, PMMA or PMMA-PU, having nanoparticles, such as, without limitation, reduced graphene oxide or SiO2, embedded therein. The electronic device may further include a second coating layer including a second polymer material (such as, without limitation, PMMA or PMMA-PU without nanoparticles) positioned between the coating layer and the assembly.

Abstract: An organic light emitting diode (OLED) lighting apparatus capable of improving lighting efficiency and lifetime by maximizing a light emitting area is disclosed. The OLED lighting apparatus may include a first electrode, which is provided with an embossing pattern at an interface at which the first electrode contacts an overcoat layer on a substrate. The first electrode may be made of a high refractive transparent conductive material, and may be arranged in an entire active area of the OLED lighting apparatus. The OLED lighting apparatus can improve light extraction efficiency through a light scattering due to a microlens effect through the first electrode provided with the embossing pattern, which facilitates elimination of a light extraction layer arranged at the interface between the substrate and the overcoat layer, thereby reducing a process yield and manufacturing cost.

Abstract: The present application relates to a packaging leadframe and a packaging structure. The packaging leadframe includes a substrate layer and a sidewall structure. A surface of the substrate layer is provided with at least one metal bump structure, a circuit layer also is laid on the surface of the substrate layer and can be electrically coupled with a LED chip. The sidewall structure is disposed on the surface with the metal bump structure, and includes a halocarbon polymer matrix and a plurality of light reflective particles uniformly mixed together. The halocarbon polymer may be poly tetra fluoroethylene or polyvinylidene fluoride. In this regard, the packaging leadframe has high reflectivity to ultraviolet light and good resistance to ultraviolet radiation.

Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.

Abstract: Aspects generally relate to tuning a guard ring in an integrated circuit. A guard ring with a gap surrounds a circuit. The level of isolation provided by the guard ring at a particular frequency can be adjusted by coupling a tuning circuit cross the gap of the guard ring. If the circuit in the guard ring is an inductive circuit the level of inductance at a particular frequency can be adjusted by selecting the appropriate tuning circuit across the gap of the guard ring.

Abstract: A display apparatus includes a substrate having a display area and a peripheral area, wirings over the peripheral area that extend in a first through third areas, an interval between the wirings in the second area is greater than an interval between the wirings in each of the first and third areas, an insulating layer covering the wirings and having a first uneven surface corresponding to the wirings, a first conductive layer over the insulating layer and including a second uneven surface corresponding to the first uneven surface, a flat planarization layer over the first conductive layer and exposing at least a portion of the first conductive layer, a second conductive layer electrically connected to the first conductive layer, at least a portion of the second conductive layer is over the planarization layer, and a polarization plate on the second conductive layer.

Abstract: A component having a boundary element is disclosed. In an embodiment a component comprises a semiconductor chip, a housing and a reflective layer, wherein the housing has a shaped body and a base body, the shaped body laterally enclosing the base body at least in places and being different from the reflective layer. In a plan view, the base body has a free area which is uncovered by the shaped body. The free area or a bottom surface of a cavity comprises a mounting surface for the semiconductor chip, wherein the semiconductor chip is arranged on the mounting surface. The bottom surface or the free area is partially covered by the reflective layer, wherein the mounting surface is enclosed at least in regions by a boundary element which adjoins the reflective layer and is configured to prevent the semiconductor chip from being covered by the reflective layer.

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.

Abstract: A process of forming a nucleus fanning layer in a nitride semiconductor epitaxial substrate is disclosed. The process includes steps of growing: a lower layer of the nucleus forming layer on a substrate; an upper layer of the nucleus thrilling layer on the lower layer; and a nitride semiconductor layer each by the metal organic chemical vapor deposition (MOCVD) technique. The growth of the nitride semiconductor layer is done at a temperature lower than a growth temperature for the upper layer, and the growth of the upper layer is done by supplying ammonia (NH3) at a flow rate greater than the flow rate of ammonia (NH3) timing the growth of the lower layer.

Abstract: Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain.

Abstract: A display apparatus includes: a transparent substrate; a panel substrate; a light emitting diode disposed between the transparent substrate and the panel substrate; an insulation layer covering side surfaces of the light emitting diode; a first connection electrode electrically connected to the light emitting diode and disposed on the insulation layer between the insulation layer and the panel substrate; a second connection electrode on the panel substrate; and an electrode connector electrically connecting the first connection electrode to the second connection electrode, wherein the first connection electrode has an overlapping portion overlapping with the light emitting diode and a non-overlapping portion laterally extending from the overlapping portion on the insulation layer.

Abstract: Light emitting devices are described herein. A light-emitting device includes a substrate having a surface below an optical cavity, one or more light emitting diodes (LEDs) disposed above the surface of the substrate, a first wavelength-converting layer, and a second wavelength-converting layer. The first wavelength-converting layer is disposed on the surface of the substrate below the optical cavity, covers the entire surface of the substrate except for portions of the surface of the substrate that are situated underneath any of the one or more LEDs, and has a thickness that is equal to or less than a thickness of at least one of the one or more LEDs. The second wavelength-converting layer is disposed above the optical cavity.