Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a plurality of lower lines disposed over a substrate and extending in a first direction; a plurality of upper lines disposed over the lower lines and extending in a second direction crossing the first direction; a plurality of memory cells disposed between the lower lines and the upper lines and overlapping intersection regions of the lower lines and the upper lines; and an air gap located between the upper lines and extending in the second direction.

Abstract: A display apparatus including a panel substrate, and a light emitting source disposed on the panel substrate, in which the light emitting source includes a substrate, an electrode disposed on the substrate, a light emitting structure disposed on the electrode and having an n-type semiconductor layer, a p-type semiconductor layer, an n-type electrode, and a p-type electrode, a transparent electrode disposed on the light emitting structure, and an adhesive layer disposed on the light emitting structure, the n-type electrode is electrically connected to the electrode, the p-type electrode is electrically connected to the transparent electrode, and the adhesive layer is disposed between the p-type electrode and the transparent electrode.

Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.

Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.

Abstract: An electronic device includes a semiconductor substrate and a heat sink arranged on a surface of the semiconductor substrate. The heat sink includes a plurality of metal filaments that each includes a first end joined to the surface, a second end, and a body over the surface such that the body is surrounded by a coolant medium to dissipate heat. The heat sink is not part of an electrical network.

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

Abstract: An information handling system includes a printed circuit board (PCB) and an integrated circuit device. The integrated circuit device includes a substrate and a die that is bonded via a first surface of the die to a first surface of the substrate. The substrate includes a ball grid array (BGA) on the first surface of the substrate. The integrated circuit device is bonded to a first surface of the PCB via the BGA. The die is collocated with the cutout area.

Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.

Abstract: A thin film resistor (TFR) module may be formed in copper interconnect in an integrated circuit device. A pair of displacement-plated TFR heads may be formed by forming a pair of copper TFR head elements (e.g., damascene trench elements) spaced apart from each other in a dielectric region, and displacement plating a barrier region on each TFR head element to form a displacement-plated TFR head. A TFR element may be formed on the pair of displacement-plated TFR heads to define a conductive path between the pair of TFR head elements through the TFR element and through the displacement-plated barrier region on each metal TFR head. Conductive contacts may be formed connected to the pair of displacement-plated TFR heads. The displacement-plated barrier regions may protect the copper TFR heads from copper corrosion and/or diffusion, and may comprise CoWP, CoWB, Pd, CoP, Ni, Co, Ni—Co alloy, or other suitable material.

Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.

Abstract: A semiconductor device includes a die having one or more trenches on a back side of the die. The semiconductor device also includes a layer of thermally conductive material deposited on the back side of the die to fill the one or more trenches to form one or more plated trenches. The size (e.g., surface area or thickness (Z-height)) or location of the plated trenches may be determined based on one or more heat generating elements such as logic devices (CPU or GPU, for example) on an active side of the die. The thermally conductive material, which may be a metal such as copper (Cu) or silver (Ag), has a heat dissipation coefficient that is greater than a heat dissipation coefficient of a substrate of the die.

Abstract: A display apparatus includes a support substrate, a plurality of light emitting structures regularly arranged on the support substrate, and a wavelength conversion part disposed on the plurality of light emitting structures. The wavelength conversion part includes light transmitting portions and blocking portions, the light transmitting portions being disposed on the light emitting structures, respectively, and each of the light transmitting portions including a phosphor for converting a wavelength of light emitted from the corresponding light emitting structure. The support substrate includes a plurality of conductive patterns electrically connected to the light emitting structures, and the light emitting structures are coupled to the plurality of conductive patterns.

Abstract: A semiconductor device package having a thermal dissipation feature is provided. The semiconductor device package includes a package substrate. A semiconductor die is mounted on a first surface of the package substrate. A first conductive connector is affixed to a first connector pad of the package substrate. A conformal thermal conductive layer is applied on the semiconductor die and a portion of the first surface of the package substrate. The conformal thermal conductive layer is configured and arranged as a thermal conduction path between the semiconductor die and the first conductive connector.

Abstract: Some embodiments relate to a semiconductor structure including a conductive wire disposed within a first dielectric structure. An etch stop layer overlies the first dielectric structure. A dielectric capping layer is disposed between an upper surface of the conductive wire and the etch stop layer. An upper dielectric layer is disposed along sidewalls of the conductive wire and an upper surface of the etch stop layer. The upper dielectric layer contacts an upper surface of the dielectric capping layer and has a top surface vertically above the etch stop layer.

Abstract: An intelligent power module packaging structure includes an insulated heat dissipation substrate, a plurality of power devices, a control chip, a lead frame, and an encapsulant. The insulated heat dissipation substrate has a first surface and a second surface opposite to the first surface. The power devices are disposed on the first surface. The control chip is disposed on the first surface. The control chip provides a gate driver function for driving the power devices and a pulse width modulation function. The lead frame is bonded onto the first surface. The power devices are electrically connected to the control chip and the lead frame. The encapsulant at least encapsulates the power devices, the control chip, and a portion of the lead frame, and the second surface is entirely or partially exposed outside the encapsulant.

Abstract: The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.