Abstract: A fabrication method produces a mechanically patterned layer of group III-nitride. The method includes providing a crystalline substrate and forming a first layer of a first group III-nitride on a planar surface of the substrate. The first layer has a single polarity and also has a pattern of holes or trenches that expose a portion of the substrate. The method includes then, epitaxially growing a second layer of a second group III-nitride over the first layer and the exposed portion of substrate. The first and second group III-nitrides have different alloy compositions. The method also includes subjecting the second layer to an aqueous solution of base to mechanically pattern the second layer.

Abstract: A method for manufacturing a current perpendicular to plane magnetoresistive sensor that allows for dynamic adjustment of free layer biasing to compensate for variations in thickness of an electrically insulating layer that separates the hard bias layers from the free layer. During fabrication of the sensor, the actual thickness of the insulation layers is measured. Then, to maintain a desired magnetic stabilization of the free layer one of three options can be utilized. Option one; adjust the stripe height target to maintain the desired magnetic stabilization. Option two; adjust the hard magnet thickness to maintain the desired magnetic stabilization. Option three; use a combination of option one and option two, adjusting both the stripe height target and the hard magnet thickness to maintain the desired magnetic stabilization.

Abstract: Method for manufacturing an electronic module, which electronic module includes a component (6), which has contact areas (17), which are connected electrically to a conductor-pattern layer (14). The manufacture according to the method starts from a layered membrane, which comprises at least a conductor layer (4) and an insulator layer (10) on the first surface of the conductor layer (4). Contact openings (17), the mutual positions of which correspond to the mutual positions of the contact areas (7) of the component (6), and which penetrate both the conductor layer (4) and the insulator layer (10), are made in the membrane. After the manufacture of the contact openings (17), the component (6) is attached to the surface of the insulator layer (10), in such a way that the contact areas (7) of the component (6) line up next to the contact openings (17).

Abstract: A manufacturing method of a silicon nozzle plate, having; a film forming process to provide the film representing an etching mask for etching the silicon substrate on a surface of the silicon substrate; a pattern film forming to form a pattern film by partially removing the film based on a nozzle hole forming pattern and an outer shape forming pattern; a silicon substrate etching process to form nozzle holes based on the nozzle hole forming pattern representing the etching mask, and to form a half etching portion at least in a part of the silicon substrate based on the outer shape forming pattern; and a silicon substrate separating process to separate the silicon substrate by splitting along the half etching portion.

Abstract: Provided is a dry etching method for an oxide semiconductor film made of In—Ga—Zn—O, in which an etching gas containing a hydrocarbon is used in a dry etching process for the oxide semiconductor film made of In—Ga—Zn—O formed on a substrate.

Abstract: By performing plasma etching on the second surface of a semiconductor wafer on the first surface of which an insulating film is placed in dividing regions and on the second surface of which a mask for defining the dividing regions are placed, the second surface being located opposite from the first surface, the insulating film is exposed from an etching bottom portion by removing portions that correspond to the dividing regions. Subsequently, by continuously performing the plasma etching in the state in which the exposed surfaces of the insulating film are charged with electric charge due to ions in the plasma, corner portions put in contact with the insulating film are removed. Subsequently, by removing the mask and thereafter performing plasma etching on the second surface, corner portions located on the second surface side are removed.

Abstract: A target layer comprising at least one degradable material is deposited on a support. Nanotubes are then formed on the degradable material of the target layer before deposition of an insulating layer is performed. Degradation of the degradable material and elimination of degradation sub-products are then performed by means of the nanotubes passing through the insulating layer thus forming air gaps in the target layer.

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including forming a film on a surface of a substrate, the film designed to prevent the seeding of an electroless plating catalyst, laser ablating the surface of the substrate through the film to form trenches, and seeding the surface of the substrate with an electroless plating catalyst. Other embodiments are also disclosed and claimed.

Abstract: An exposure mask for forming a G-type active region with a double patterning technology includes a bar shaped first light-blocking pattern to define an I-type active region, and an island shaped second light-blocking pattern to define a bit line contact region. The first light-blocking pattern and the second light-blocking pattern are arranged alternately.

Abstract: A method for forming hard mask patterns includes, sequentially forming first, second, and third hard mask layers formed of materials having different etching selectivities on a substrate, forming first sacrificial patterns having a first pitch therebetween on the third hard mask layer, forming fourth hard mask patterns with a second pitch between the first sacrificial patterns, the second pitch being substantially equal to about ½ of the first pitch, patterning the third hard mask layer to form third hard mask patterns using the fourth hard mask patterns as an etch mask, patterning the second hard mask layer to form second hard mask patterns using the third and fourth hard mask patterns as an etch mask, and patterning the first hard mask layer to form first hard mask patterns with the second pitch therebetween using the second and third hard mask patterns as an etch mask.

Abstract: Methods for improving adhesion between a shape memory alloy and a polymeric material include functionalizing a surface of the shape memory polymer with a phosphorous containing compound or an organosilane coupling agent. Other methods include surface texturing the shape memory alloy surface, independently or in combination with the functionalization.

Abstract: In a method of forming a pattern and a method of forming a capacitor, an oxide layer pattern having an opening is formed on a substrate. A conductive layer is formed on the oxide layer pattern and the bottom and sidewalls of the opening. A buffer layer pattern is formed in the opening having the conductive layer, the buffer layer pattern including a siloxane polymer. The conductive layer on the oxide layer pattern is selectively removed using the buffer layer pattern as an etching mask. A conductive pattern having a cylindrical shape can be formed on the substrate. The method of forming a pattern may simplify manufacturing processes for a capacitor and a semiconductor device, and may improve their efficiencies.

Abstract: The spectral reflectance spectrum of an object of polishing that has reached the polishing endpoint is found ahead of time, the spectral reflectance spectrum of the object of polishing is found during polishing, and the correlation coefficient of these is seen as parameter 1. Meanwhile, the sum of the absolute values of the difference between the first order differentials of these is seen as parameter 2. Then, when parameter 1 is in a range exceeding a specific value, and parameter 2 is at its minimum, it is concluded that the polishing endpoint has been reached. Thus, it is possible to provide a method for detecting the polishing endpoint in a highly reliable CMP polishing apparatus.

Abstract: A method for making a master mold that is used in the nanoimprinting process to make patterned-media disks with patterned data islands uses guided self-assembly of a block copolymer into its components. Conventional or e-beam lithography is used to first form a pattern of generally radial stripes on a substrate, with the stripes being grouped into annular zones or bands. A block copolymer material is then deposited on the pattern, resulting in guided self-assembly of the block copolymer into its components to multiply the generally radial stripes into generally radial lines. Various methods, including conventional lithography, guided self-assembly of a second block copolymer, and e-beam lithography, are then used to form concentric rings over the generally radial lines. After etching and resist removal, the master mold has a pattern of either pillars or holes, depending on the method used.

Abstract: Chalcogenide devices are delineated and sidewalls of the devices are sealed, in an anaerobic and/or anhydrous environment environment. Throughout the delineation and sealing steps, and any intervening steps, the sidewalls are not exposed to oxygen or water. In an illustrative embodiment, a cluster tool includes an etching tool and a sealing/deposition tool configured to etch and seal the chalcogenide devices and to maintain the devices in an anaerobic and/or anhydrous environment throughout the process.

Abstract: The present invention provides a regeneration process of the etching solution for the silicon nitride film, applying phosphoric acid aqueous solution, wherein multiple numbers of filters are connected to the piping path of etching solution extracted from the etching tank by switching alternately in parallel or in series; in both cases that said multiple numbers of filters are connected in parallel or in series, said extracted etching solution being supplied to a filter with a filter element of a high silicon removal rate of silicon compounds with already deposited silicon compounds, thus maintaining a high silicon removal rate of silicon compounds.

Abstract: A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.

Abstract: The present invention discloses a polishing slurry, wherein said polishing slurry comprises a carrier and functionalized alumina grains. The polishing slurry, which comprises functionalized alumina grains having desirable dispersibility, has desirable stability and is able to lower the defect rate of the substrate surface, improve the surface quality, decrease the total metal loss and enlarge the variation range of the technical parameters.

Abstract: A method for removing undesirable contaminants from a chip passivation layer surface without creating SiO2 particles on the passivation layer, wherein the undesirable contaminants include graphitic layers and fluorinated layers. The use of N2 plasma with optimized plasma parameters can remove through etching both the graphitic and fluorinated organic layers. The best condition for the N2 plasma treatment is to use a relatively low-power within the range of 100-200 W and a relatively high vacuum pressure of N2 in the range of 500-750 mTorr.

Abstract: A WC substrate 7 is etched by using plasma 50 generated from a gas including a chlorine atom.