Abstract: A large number of processor cells 11, the majority of which are standard cells 12 and others special cells 13, are connected to a communication network 14 in the form of several binary trees. The cells 11 are connected at the leaf positions of the binary trees, and the nodes of the binary trees are formed by switching circuits that allow individual cells to control the formation of signal paths through the nodes. In operation, cells may be in a waiting state, a free state, a calling state, searching state, a communicating state, or an internal operation state. Cells 12 in the free state transmit a free signal into the network 14. Cells 12 or 13 in a searching state transmit a searching signal into the network 14 where, on meeting a free signal at a node, a route is formed from the searching state cell to a free state cell. A calling state cell 12 establishes, with a calling signal, a route through the network 14 to another cell identified by destination information in the calling signal.

Abstract: According to the present invention, a 3D connectivity-conserved grain-structured processing architecture uses connectable massively parallel processors. A 3D grain-structured processing architecture is provided. The 3D links of the grain-structured processing architecture provide direct local communication as well as global communication for voxel processing and analysis tasks. A novel transport naming scheme which is scalable in any three-dimension direction and the local/global communication protocol are disclosed. The 3D volumetric data set is first divided into a set of voxel sub-cubes. Each voxel subcube is processed by a processor element of the grain-structured processing architecture. Data discontinuity is produced after performing local operations in a massively parallel processors environment and requires replacing the resulted voxel data set in the overlap region for each voxel sub-cube.

Abstract: A computer-based system, such as a value printing system, has a host data processor having at least one disk drive that includes a first read/write head for reading data from and for writing data to a removable data recording disk. The system further includes a printer, coupled to the host data processor and responsive thereto, for printing indicia indicative of a monetary value. The system further includes a removable data recording disk having an integral data processor including a memory for storing data expressive of a monetary value associated with printed indicia. The integral data processor further includes a second read/write head coupled to the recording medium for communicating with the host data processor through the first read/write head.

Abstract: The invention establishes the context in which data exchanged between dissimilar relational database management systems can be mutually understood and preserved, and data conversions can be minimized. The invention accomplishes this by establishing layers of descriptive information which isolate machine characteristics, levels of support software, and user data descriptions. Optimized processing is achieved by processing the different descriptor levels at different times during the development and execution of the database management systems. Minimal descriptive information is exchanged between the cooperating database management systems. Any data conversions that may be necessary are done only by the receiver of the data, and only at the point where it is necessary to have the data represented in the receiver's native format for processing.

Abstract: Apparatus is provided for creating an entry point into a set of execution subsequences of instructions created from a sequential execution sequence at a point other than the beginning, the subsequences being executable asynchronously in parallel on separate processing elements. The creation of intermediate entry points allows the set of execution subsequences to be used to execute different portions of the sequential execution sequence asynchronously in parallel whenever one of those portions reoccurs in another execution sequence of instructions. In the preferred embodiment, execution sequences are processed in two modes of execution, one mode being used not only to execute instructions but also simultaneously to parallelize into a set of subsequences any instruction sequences which have not already been parallelized, while the second mode is used to execute parallelized instruction sequences in parallel.

Abstract: A single-chip microcomputer includes a microprocessor, a subprocessor for performing peripheral functions, an external port for controlling an input/output operation from/to an external device and a multi-functional logic-in-memory for inputting a plurality of data from at least one of the microprocessor, the subprocessor and the external port and selecting write data from among the plurality of data in accordance with predetermined priorities.

Abstract: A field compositor, with a regular and systematic structure, that merges fields of data together to compose new data words. Starting from a basic cell, the field compositor merges longer words by connecting more of the basic cells together in a systematic and orderly fashion. The cells are connected in a regular structure so that routing data through the compositor can be done in a similarly regular manner. The basic cell of a one-dimensional regular array has three control inputs to control two outputs, one being a data output; depending on the logic levels presented to the three inputs, data from the first or the second set of data are selected to be the data output of the cell. The basic cell of a two-dimension regular array has five control inputs and two outputs, one being a data output; depending on the logic levels of the five control inputs, data from the first or the second set of data are selected to be the data output of the cell.

Abstract: A document processing apparatus which has a keyboard for inputting characters and instructions. The apparatus includes a memory that randomly stores the inputted characters as titles and documents. The memory includes a field associated with each of the titles for storing an evaluation value indicating an order for the sequential display of the titles. The evaluation value is generated by comparing each of the titles to each other to determine the order of the sequential display. The apparatus in response to the inputted instructions sequentially displays the titles in a forward or a reverse sequence.

Abstract: The present invention provides a data train generating system with no restriction on the number of data which can be generated at a high data rate by use of low-speed memory. A conditional mode may be used to change the data output sequence at an arbitrary time whereby the output is substantially uneffected by the operational speed of the memory used and the waiting time for the change to occur is reduced.

Abstract: A one-chip microcomputer according to the present invention is provided with an initial reset circuit for producing a first initial reset signal having a first reset period and a second initial reset signal having a second reset period which is longer than the first reset period, an access circuit for gaining access to an address in a nonvolatile memory such as a built-in ROM to read data therefrom, and I/O buffer circuits. A storage circuit and an I/O buffer connected to a programmable I/O terminal are provided in the I/O buffer circuit and a function of the I/O terminal with options is selected in conformity with the data set in the storage circuit. The data stored at a predetermined address in the nonvolatile memory is transferred to the storage circuit by operating the access circuit until the termination of the reset period of the second initial reset signal after the termination of the first reset period of the first initial reset signal.

Abstract: A data processor having memory requesters to execute instructions, an instruction hold unit disposed for each resource to hold an instruction being executed in the resource and instructions to be executed therein, and execution control units to cause, in a case where an execution completion report of an instruction being executed in either one of the resources is received, an instruction held in an instruction hold unit corresponding to the resource to be immediately executed, thereby successively supplying the respective resources with data items to be employed for executions of the consecutive instructions in the resources.

Abstract: A model information control system ("MICS") is used in conjunction with a user-defined information model and one or more conventional information system program modules or "functions" to execute business applications. The MICS includes an event-action-state machine that manipulates the user-defined information model and the functions.

Abstract: A multiplexed address and data bus system provides a minimum pin count with byte enable and burst address counter support. The partitioning of the address bus includes separate byte enables to indicate specifically which bytes of the word are being accessed, and two independent address lines which can function as a counter to support the burst refill. Both block reads or single datum transfers are handled similarly: a single addressing phase with multiple data phases; and all addresses in the memory system; are derived directly from the same pins regardless of whether it is a block read or not. The system allows for low cost packaging while maintaining a variety of system capabilities.

Abstract: A homebus system for permitting use of a twisted pair line homebus to both homebus equipment and integrated service digital network (ISDN) interface equipment. The homebus system includes a homebus controller for controlling access to the twisted pair line homebus so as to selectively connect and disconnect a digital service unit for communication between a digital network and the ISDN interface equipment connected to said twisted pair line homebus via an information plug socket.

Abstract: A method for signaling the type of access sought by a microprocessor to external memory. A microprocessor can read from or write into external memory. When the microprocessor initiates a read or write cycle, access signals indicating: the read or write cycle, the lower order address bits of the sought after code or data, whether code or data is sought, and bit-width of the sought after code or data, are provided to the inventions byte enable chaser circuit. If a read cycle has been initiated the byte enable chaser circuit encodes the signals into predetermined bit patterns and outputs the bit patterns on the microprocessor's byte enable signal pins. The bit-patterns are available for each bus cycle and specify whether code or data is sought, the length of the sought string, and the lower order address bits of the strings address. If a write cycle is initiated the byte enable signed pins indicate which byte(s) of the data bus are to be written into memory.

Abstract: A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof.

Abstract: A digital computer system has a central processor unit (CPU) and a store queue facility. The store queue facility receives full digital words or segments thereof (bytes) for intermediate storage prior to storage in an addressable unit such as a dynamic random access memory (DRAM). The store queue facility has a plurality of registers for storing digital words and bytes for storage at different, discreet addresses in the addressable unit. The store queue has circuitry for assembling bytes into a digital word or into a plurality of bytes for ultimate storage in the addressable unit. Some combinations of bytes are not valid and will therefore not be entered together in a single digital word.

Abstract: A method is provided for adding extended functions to a multiprocessor system, specifically, functions that may be called from programming running on a first processor and executed by a second processor. The function may have an argument that requires a large amount of argument data. Each extended function is associated with a special entry point command, which is in turn, associated with a communications routine that handles the transfer of the large argument data from the first processor to the second processor in bursts.

Abstract: A multithreaded parallel data processing system has at least one processing element for processing multiple threads of computation. Threads are described by thread descriptors which are stored while waiting to be processed in a thread descriptor storage. Thread descriptors are comprised of an instruction pointer and a frame pointer. The instruction pointer points to the next instruction to be executed, and the frame pointer points to a frame of memory locations that the next instruction will operate on. Included within the instruction on set of the at least one processing element is a load instruction that loads global data into local processing element memory that is performed to two phases: a request phase and a response phase. Also included are instructions to fork a thread into two threads and to join two threads into a single thread.

Abstract: A digital computer having a plurality of message generating elements each generating and receiving messages and a network for transferring messages among the message generating elements. The network includes a plurality of node clusters interconnected in a tree pattern from a lower leaf level to an upper root level, each node cluster including at least one node group with node clusters in a level above at least one predetermined level having a larger number of node groups than node clusters of the predetermined level for transferring messages among the message generating elements.