Abstract: An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.
Type:
Grant
Filed:
July 14, 1983
Date of Patent:
August 27, 1985
Assignee:
Burroughs Corporation
Inventors:
Burton L. Levin, Andrew E. Phelps, Hanan Potash
Abstract: In known speech recognition systems, processors and methods, utterances are analyzed to obtain a set of reference signals. An unknown signal may be compared with the reference signals. The unknown signal may be said to be the reference signal with which it most closely corresponds as defined by some correspondence measure. Known signal recognition arrangements using multiple processor cells tend to be expensive, in part because they tend to use many processor cells.The disclosed system, processor and method contemplate an arrangement including an array of processor cells for time warping an unknown signal having m elements with respect to a reference signal having n elements or vice versa. The cells, responsive to control signals on a control diagonal, generate the correspondence measure. As the signals propagate through the array, the instant arrangement recirculates signals from cells near one (or first) periphery of the arrangement, e.g.
Type:
Grant
Filed:
June 14, 1982
Date of Patent:
April 2, 1985
Assignee:
AT&T Bell Laboratories
Inventors:
Bryan D. Ackland, David J. Burr, Neil H. E. Weste