Abstract: An apparatus is programmed to automatically remove timing hazards from a circuit design. The apparatus identifies certain level sensitive storage circuit elements in the circuit design. The identified level sensitive storage circuit elements are those having timing hazards. The timing hazards arise as a result of potential skews between the reference signal for the circuit design and the synchronization signal controlling each storage circuit element. A skew, introduced by a gated or divided clock, cannot be assured to be within a design tolerance limit. Therefore, the program enables the apparatus to transform the identified level sensitive storage circuit elements into level sensitive storage circuit elements controlled by synchronization signals that do not have potential skews with respect to the reference signal of the circuit design. The transformation, however, is accomplished without altering the functionality of the circuit design.

Abstract: An apparatus for controlling a vehicle active suspension system having a plurality of actuatable hydraulic motors, each corner having a motor connecting the sprung mass with its associated unsprung mass. Each motor has an associated spool valve for connecting either of two expandable fluid chambers of said motor to a pump or reservoir. Each corner has an associated force sensor for sensing the force value between its associated unsprung mass and the sprung mass. An analog, closed force loop control circuit provides a valve control signal having a value functionally related to the difference between a sensed force value and a desired force value for a selected corner. The closed loop control circuit includes a variable gain amplifier for controlling the value of the valve control signal as a function of the frequency of variations in the difference between the sensed force value and the desired force value on the selected corner.

Abstract: In a logic simulator for simulating a logic circuit described by sentences, each specifying at least one operation and at least two variables which should be subjected to the operation, a model memory memorizes operators for carrying out the operations for the sentences. A variable memory memorizes initial values of the variables for the sentences. A sentence calculating unit calculates one of the sentences as a current sentence at a time to produce a result of calculation by using those of the operators and the initial values which are related to the current sentence. A data or result memory memorizes previous data or initial result values calculated before calculation of the current sentence. The result of calculation is substituted for those of the previous data or the initial result values which are related to the current sentences.