Abstract: A sense amplifier comprises a transistor configured to be switched with a column select line to pass a bit line equalization voltage, an array equalize device coupled to the transistor for receiving the bit line equalization voltage, a sense amplifier equalize device, a multiplexer coupled between the sense amplifier equalize device and the array equalize device, and a cross-coupled amplifier latch coupled to the sense amplifier equalize device.

Abstract: Devices and methods are presented for providing an AC signal delay. By control charging the interelectrode capacitance of the devices the length of the rise and fall times of a switching device can be increased and the signal accordingly delayed. Electrical circuitry is provided having a variable AC signal control means and a capacitor-switch joined to the signal control means. Changing the bias of the capacitor-switch will terminate the time delay. A signal entering the circuit input is therefore adjustably delayed and exactly reproduced prior to exiting the circuitry.