Abstract: A device includes a clock generator configured to generate a root clock signal based on an input clock signal and a clock generator divider integer setting. The device also includes a first component coupled to the clock generator and configured to generate a first component clock signal based on the root clock signal and a first component divider integer setting. The device also includes a second component coupled to the clock generator and configured to generate a second component clock signal based on the root clock signal and a second component divider integer setting. The device also includes sync circuitry coupled to each of the clock generator, the first component, and the second component, wherein the sync circuitry is configured to perform synchronized adjustments to the root clock signal, the first component clock signal, and the second component clock signal.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: An electronic device is disclosed, including: a display, a processor, and a memory operatively connected to the processor, the memory storing instructions and a plurality of applications installed in the electronic device, wherein the instructions, which when executed, cause the processor to: identify states for each of the plurality of applications, the states each including one of an enabled state, a sleep state, or a disabled state, wherein applications in the sleep state are grouped into a first application group, and applications in the disabled state are grouped into a second application group, execute a first application to display a first field, a second field, and a third field including a selectable object via the display, and based on a first user input selecting the selectable object, re-identity the states of each of the plurality of applications to update the first application group and the second application group.

Abstract: Changes in a clock signal, such as phase changes or resets, may propagate glitches, such as shortened clock cycles that may cause undesired effects in subsequent circuitry, to circuitry reliant upon the clock signal. Glitches in the clock signal may not allow a circuit component to finish operating before the shortened next clock cycle arrives, which may cause an unknown or error state in the circuit component. As such, clock change circuitry may reduce or eliminate glitches by holding the clock signal in a particular state (e.g., logically low) while the change occurs, and release the clock signal afterwards, effectively skipping or overall reducing potentially glitched clock cycles.

Abstract: A topology of bi-directional multi-output multi-function converter is designed in a BBU. The concept of bi-directional multi-function multi-output converter may be designed for the application of BBUs in a data center to provide multiple control functionalizes, such as battery discharging, battery charging, fan speed control, pump control, as well as providing power for multiple components/devices simultaneously. The proposed converter has two characteristics: bi-direction and multi-output. With the function of bi-direction, the battery discharging and charging can be accomplished with the same converter. With the function of multi-output, different rails of output voltages or power can be applied to different components or devices in BBU, such as fan, pump, control IC chip, sensors and etc.

Abstract: Techniques for memory management of a data processing system are described herein. According to one embodiment, a memory usage monitor executed by a processor of a data processing system monitors memory usages of groups of programs running within a memory of the data processing system. In response to determining that a first memory usage of a first group of the programs exceeds a first predetermined threshold, a user level reboot is performed in which one or more applications running within a user space of an operating system of the data processing system are terminated and relaunched. In response to determining that a second memory usage of a second group of the programs exceeds a second predetermined threshold, a system level reboot is performed in which one or more system components running within a kernel space of the operating system are terminated and relaunched.

Abstract: A method of an electronic device are provided in which current consumption for one or more components of the electronic device is compared with a predetermined current. A first surface temperature of the electronic device is determined based on the comparison and power consumption of the one or more components. A location is detected where heat corresponding to the first surface temperature is generated. A second surface temperature of the electronic device is obtained based on power consumption of a component disposed in the electronic device corresponding to the location where the heat is generated. A target temperature is set based on the obtained second surface temperature. The component is controlled to reduce the power consumption of the component based on the target temperature.

Abstract: A kexec-based system update process wherein user-specific data is transferred on reboot of the second kernel. Upon initializing kexec load, buffer memory is assigned to the second kernel and the system loads control pages of fixed size for the second kernel boot, and also loads user-specific data onto extended control pages of variable size. Upon boot of the second kernel, the user-specific data is extracted from the extended control pages and transferred to the corresponding applications.

Abstract: In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

Abstract: A high performance (HPC) system is described. The system includes a head node comprising one or more processors to execute a configuration manager to receive a database trigger and transmit configuration updates including configuration input data and a plurality of compute nodes, communicatively coupled to the head node, each compute node comprising one or more processors to execute a client to receive a configuration update, generate a configuration file based on configuration input data included in the configuration update and configure the compute node based on the configuration file.

Abstract: An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.

Abstract: The present disclosure relates to systems and methods for elastic delivery, processing, and storage for wearable devices based on system resources. For example, a wearable apparatus may have at least one battery; at least one sensor configured to measure at least one property associated with a user of the wearable apparatus; at least one memory storing measurements from the at least one sensor and instructions; at least one transmitter configured to send data to a device remote from the wearable apparatus; and at least one processor configured to execute the instructions to: receive, from the at least one battery, an indicator of a charge; and based on the received indicator, sending a command to the at least one sensor to operate in a low-power mode or a high-power mode, the low-power mode having. a lower sampling rate than the high-power mode.

Abstract: A system incorporating a smartphone comprising a smartphone and add-on device coupled to each other via combined data/power interface, wherein the smartphone comprises a rechargeable battery connected to battery protection circuitry and the add-on device optionally comprises a rechargeable battery connected to battery protection circuitry as well, the combined data/power interface comprises: one or more data pins for transferring data between the smartphone and the add-on device; one or more regulated power delivery pins; and one or more protected-battery power delivery pins, wherein the regulated power delivery pins are used to charge the battery of the smartphone from an external charger coupled to the add-on device, the batteries are connected to the battery protection circuitries that is configured to protect the battery by cutoff or limit the current or voltage on the battery electrodes, the protected-battery power delivery pins are connected to the battery protection circuitries of the smartphone or add

Abstract: Systems and methods for clock recovery are disclosed. The method comprises generating, by a first dynamic phase interpolator, a first center clock signal, and generating, by a second dynamic phase interpolator, a second center clock signal. The method further comprises outputting, by a static phase interpolator, an edge clock signal based on the first and second center clock signals.

Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to a transmit wake time.

Abstract: A computing device has an energy storage device system with multiple energy storage devices. Various different criteria are used to determine which one or more of the multiple energy storage devices to charge or discharge at any given time to provide power to the computing device. The criteria can include characteristics of the energy storage devices as well as hardware and/or physical characteristics of the computing device, characteristics of the energy storage devices and/or the computing device that change while the computing device operates, and predicted behavior or usage of the computing device. These criteria are evaluated during operation of the computing device, and the appropriate energy storage device(s) from which to draw power or to charge at any given time based on these criteria are determined.

Abstract: Disclosed are methods and systems to improve the time synchronization of power distribution systems and/or other distributed device networks. The disclosure relates to nesting selection algorithms to elect a grand master clock from among groups of devices in a network.

Abstract: A referenceless frequency acquisition scheme locks to an unknown data frequency by feedback of sampled data to a digitally controlled oscillator (DCO). A received data signal is converted to deserialized outputs, then by a phase detector to symbol streams of phase updates. Each symbol stream is converted to a lower rate sum, for which absolute values are computed and periodically summed. Absolute value sums are obtained for each frequency over a range of test frequencies to obtain totals, each corresponding to a different test frequency. A critical value is determined from among the totals. The DCO is set to the test frequency corresponding to the critical value as a coarse approximation for the unknown frequency.

Abstract: A computing environment includes multiple client devices that may each be configured to serve a particular function within the computing environment. The client devices are each coupled to a client management server that communicates with and manages functions of the client devices. When a client device first boots, the client management server communicates with the client device over a network in order to provision the client device with an enrollment image. Using the enrollment image, a client device can become enrolled with the client management server. Once enrolled, the client management server can provision the client device with a functional operating system image. The functional operating system image can support device applications that require a restricted number of runtime states within the client device. A new functional operating system image is downloaded from the client management server and installed on the client device each time the device is rebooted.

Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).