Patents Examined by Philip Guyton
  • Patent number: 11953979
    Abstract: Systems and methods include acquisition of a database system workload comprising a plurality of database queries, replay of the database system workload on each of a plurality of database systems to generate a plurality of failed events, each of the plurality of failed events associated with a plurality of attributes, assignment of a root cause to each of the plurality of failed events, and training of a classification model, based on the plurality of failed events an assigned root causes, to infer an output root cause based on an input plurality of attributes.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: April 9, 2024
    Assignee: SAP SE
    Inventors: Neetha Jambigi, Joshua Hammesfahr, Felix Schabernack, Leonardo Silva Rosa
  • Patent number: 11947415
    Abstract: According to various embodiments, a method, medium, and system for exporting log messages related to a particular job running in a micro services system is described in this disclosure. The method uses a mapping table to narrow down the search scope for finding relevant log files. The mapping table maps a job attribute combination to one or more micro services, and thus will direct the search for relevant log messages only to those log files related to the one or more micro services. The search scope can be further narrowed down using a start time and end time of the job. Once the relevant log files are found, log messages containing an identifier of the job can be extracted from the relevant log files for display or for a user to download. The mapping table can be automatically generated by parsing through historical files in a system non-busy time.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 2, 2024
    Assignee: DELL PRODUCTS L.P.
    Inventors: Mengze Liao, Pankaj Pande, Jinjin Wang, Scott Quesnelle
  • Patent number: 11940873
    Abstract: Apparatuses, systems, and methods for low latency parity for a memory device include a controller configured to accumulate, in a memory buffer, combined parity data for a plurality of regions of memory of a memory device in response to write operations for the plurality of regions of memory. The controller is configured to perform a recovery operation for a region of memory in response to determining that a latency setting for the region satisfies a latency threshold. The controller is configured to service a read request for data from the region based on a recovery operation to satisfy the latency setting.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: March 26, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Vimal Kumar Jain
  • Patent number: 11940887
    Abstract: Systems, apparatus and methods are provided for performing cache program operations in a non-volatile storage system. A method may comprise issuing a first cache program operation from a storage controller to a non-volatile storage device to write data to a first regular block, writing the data to the first regular block and a copy of the data to a backup block, determining that a program error has occurred while writing the data to the first regular block, asserting the program error to the storage controller, retrieving a mapping between the first regular block and the backup block, issuing a read operation to read the copy of the data from the backup block, reading the copy of the data from the backup block and issuing a second cache program operation to write the data to a second regular block and marking the first regular block as defective.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: March 26, 2024
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Gang Zhao, Lin Chen, Jie Chen, Qun Zhao
  • Patent number: 11940891
    Abstract: A method, system, and apparatus for fault detection in a microprocessor-based system uses a serial data communication protocol for communications between a peripheral device and a controller. Peripheral device interface circuitry is adapted to intermittently receive input serial data frames from the controller using the serial communication protocol and to intermittently send output serial data frames to the controller using the serial communication protocol. Each output serial data frame includes one or more status bits representing communication status data and one or more data bits representing peripheral device data. The status bits and the data bits are serially followed by at least one fault bit that indicates whether a fault is detected during sending of the output serial data frame.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Scott Allen Monroe
  • Patent number: 11933847
    Abstract: The invention relates to an apparatus and a system for debugging a solid-state disk (SSD) device. The apparatus includes a Joint Test Action Group (JTAG) add-on board; and a Raspberry Pi. The Raspberry Pi includes a General-Purpose Input/Output (GPIO) interface (I/F), coupled to the JTAG add-on board; and a processing unit, coupled to the GPIO I/F. The processing unit is arranged operably to: simulate to issue a plurality of JTAG command through the GPIO I/F to the SSD device for dumping data generated by the SSD device during operation from the SSD device.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: March 19, 2024
    Assignee: SILICON MOTION, INC.
    Inventors: Han-Chih Tsai, Ming-Kun Chung
  • Patent number: 11901976
    Abstract: Methods are disclosed for improving communications on feedback transmission channels, in which there is a possibility of bit errors. The basic solutions to counter those errors are: proper design of the CSI vector quantizer indexing (i.e., the bit representation of centroid indices) in order to minimize impact of index errors, use of error detection techniques to expurgate the erroneous indices and use of other methods to recover correct indices.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: February 13, 2024
    Assignee: Wi-LAN Inc.
    Inventors: Bartosz Mielczarek, Witold A. Krzymien
  • Patent number: 11892909
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of at least one memory device of the set, wherein the failure affects stored data; notifying a host system of a change in a capacity of the set of memory devices; receiving from the host system an indication to continue at a reduced capacity; and updating the set of memory devices to change the capacity to the reduced capacity.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11868224
    Abstract: A method includes providing, when delivery of power to a memory sub-system comprising a plurality of non-volatile memory components from a main power supply is interrupted, power from an auxiliary power supply to a portion of a controller interfacing with the non-volatile memory components. The portion of the controller may utilize the power from the auxiliary power to supply to: responsive to a prediction, generated when the delivery of the power from the main power supply to the memory sub-system is interrupted, that a particular portion of the plurality of non-volatile memory components will experience an impending data loss event, perform a targeted refresh operation of data stored in the particular portion.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Nicholas T. Heath
  • Patent number: 11868203
    Abstract: A method for detecting computer issues includes identifying a target computer system. A first set of data for a first time period relating an operating metric from the target computer system are received. The operating metric is stored. A second set of data for a second time period relating to the operating metric is received. The first and second sets of data are compared. A difference between the two sets of data is identified. If the difference between the two sets of data is within a range a warning notification is displayed in a graphical user interface. An input is received in the graphical user interface in response to the warning notification being displayed.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: January 9, 2024
    Assignee: United Services Automobile Association (USAA)
    Inventors: Manuel A. Carranza, Chase T. Sekula, Mark S. Moore, Mathew P. Ringer
  • Patent number: 11853618
    Abstract: Techniques for RAID reconstruction involve: determining, from a task list, multiple stripes in a RAID that are involved in a to-be-processed task within a current task window, the task list including an external I/O request task and an internal reconstruction I/O request task, and each stripe including data on a first number of data disks and data on a second number of parity disks; reading data from the multiple stripes into a read buffer; and if data of the first number of data disks in a stripe among the multiple stripes has already been read into the read buffer, performing the internal reconstruction I/O request task on the stripe. Such a technique helps to increase the processing power and efficiency of the data storage system to recover the reconstruction of RAID stripes while coping with external I/O requests.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 26, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Qian Wu, Bo Hu, Jing Ye
  • Patent number: 11847037
    Abstract: Example implementations include a method of receiving a host command identifier associated with a host command, determining a device command associated with the host command and a memory controller device, receiving a device command timestamp corresponding to a time of the determining the device command, and determining a debug record contemporaneously with the determining the device command, the debug record including the host command identifier, a device command identifier associated with the device command, and the device command timestamp.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: December 19, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Paul Edward Hanham, Shigehiro Asano, Julien Margetts
  • Patent number: 11829270
    Abstract: Apparatus and method for a die kill and recovery sequence for a non-volatile memory (NVM). Data are stored in the NVM as data sets in garbage collection units (GCUs) that span multiple semiconductor dies. A die failure management circuit is configured to detect a die failure event associated with a selected die, and to generate a recovery strategy to accommodate the detected die failure event by selecting recovery actions to be taken in a selected sequence to maintain a current level of data transfer performance with a client device. The selected recovery actions are carried out in the selected sequence to transfer at least a portion of the user data stored in the selected die to a new replacement die, after which the selected die is decommissioned from further use. The NVM may be a flash memory of a solid-state drive (SSD).
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: November 28, 2023
    Assignee: Seagate Technology LLC
    Inventors: Stacey Secatch, Stephen H. Perlmutter, Matthew Stoering, Jonathan Henze
  • Patent number: 11829269
    Abstract: One or more aspects of the present disclosure relate to recovering at least one failed disk. In embodiments, determining a storage reserve capacity allocated for recovering at least one storage device of a storage array is determined. Zero or more storage portions from each storage device of at least one storage cluster for disk recovery are adaptively assigned based on the storage reserve capacity. The failing and/or failed disk using the assigned storage portions is recovered in response to detecting a failing and/or failed disk.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: November 28, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Kuolin Hua, Kunxiu Gao
  • Patent number: 11829279
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Martin-Thomas Grymel, David Bernard, Martin Power, Niall Hanrahan, Kevin Brady
  • Patent number: 11809288
    Abstract: A method and system for performing a flexible Byzantine fault tolerant (BFT) protocol. The method includes sending, from a client device, a proposed value to a plurality of replica devices and receiving, from at least one of the plurality of replica devices, a safe vote on the proposed value. The replica device sends the safe vote, based on a first quorum being reached, to the client device and each of the other replica devices of the plurality of replica devices. The method further includes determining that a number of received safe votes for the proposed value meets or exceeds a second quorum threshold, selecting the proposed value based on the determination, and setting a period of time within which to receive additional votes. The method further includes, based on the period of time elapsing without receiving the additional votes, committing the selected value for the single view.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: November 7, 2023
    Assignee: VMware, Inc.
    Inventors: Ittai Abraham, Dahlia Malkhi, Kartik Nayak, Ling Ren
  • Patent number: 11809274
    Abstract: Techniques are provided to recover from partial device errors of storage devices in a data storage system. A storage control system manages a storage device which comprises storage capacity that is logically partitioned into segments of equal size. The storage control system groups at least some of the segments of the storage device into a segment group. Each segment of the segment group is configured to store one or more data items and associated metadata items. The storage control system generates a parity data segment based on the segments of the segment group, and persistently stores the parity data segment in association with the segment group. In response to detecting a storage device error associated with a corrupted segment of the segment group, the storage control system utilizes the parity data segment and non-corrupted segments of the segment group to recover at least one missing data item of the corrupted segment.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 7, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Doron Tal, Yoav Peled, Itay Keller, Asaf Porath, Neta Peleg
  • Patent number: 11809880
    Abstract: Dynamically verifying ingress configuration changes is provided. A temporary ingress controller configuration is generated for an ingress configuration change set contained in an ingress configuration change set dispatcher queue of an ingress controller pod. The temporary ingress controller configuration corresponding to the ingress configuration change set is loaded into a temporary ingress controller located in a temporary ingress controller pod of the computer. A health check is performed on the temporary ingress controller pod running the temporary ingress controller with the temporary ingress controller configuration corresponding to the ingress configuration change set.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: November 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Wei Wu, Xin Peng Liu, Yue Wang, Liang Wang, Zheng Li, Biao Chai
  • Patent number: 11803436
    Abstract: A storage device and a storage system including the same are provided. The storage device includes a nonvolatile memory with a valid page and a free page; a temperature sensor configured to sense a temperature of the nonvolatile memory; and a storage controller configured to implement: a patrol read module configured to read valid data stored in the valid page and identify a number of errors in the read valid data according to a set time period, and a retention module configured to, based on the temperature or the number of errors, read the valid data stored in the valid page, and write the valid data to the free page while controlling a threshold voltage distribution width corresponding to a value of the valid data written to the free page.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: October 31, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul Ho Lee, Ki Jong Nam, Won-Gi Hong
  • Patent number: 11789820
    Abstract: A system and method for preventing a hang up after initiation of a watch dog time out in a computer system. A start-up routine is run via a basic input output system (BIOS). The routine applies settings for hardware components. It is determined if a watch dog timer triggered a restart from timing out when the start-up routine ran previously. The system checks a database storing settings for each of the plurality of hardware components for a proper setting for the hardware components if the watch dog timer triggered the restart. The system applies the settings from the database for the hardware components to avoid another hang up.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: October 17, 2023
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yung-Fong Chou, Kuo-Chun Liao, Zhen-An Hung, Mei-Chen Wang