Abstract: A group III-V material CMOS device may have NMOS and PMOS portions that are substantially the same through several of their layers. This may make the CMOS device easy to make and prevent coefficient of thermal expansion mismatches between the NMOS and PMOS portions.

Abstract: To form a polycrystalline silicon film having a grain size of 1 ?m or greater by means of laser annealing. A beam emitted from a laser apparatus (101) is split in two by a half mirror. The split beams are processed into linear shapes by cylindrical lenses (102) to (105), and (207), then simultaneously irradiate an irradiation surface (209). If an amorphous silicon film formed on a glass substrate is disposed on the irradiation surface (209), an area will be irradiated by both a linear shape beam entering from a front surface and a linear shape beam that has transmitted through the glass surface. Both linear shape beams irradiate the same area to thereby crystallize the amorphous silicon film.

Abstract: A process for forming a catalyst layer for carbon nanotube growth comprising forming a catalyst layer having a first and second portion over one of a cathode metal layer or a ballast resistor layer; patterning a photoresist over the first portion; etching the second portion with a chlorine/argon plasma; removing the photoresist with an ash process; and removing the veils and preparing the surface for carbon nanotube growth with a semi-aqueous hydroxylamine solution.

Abstract: Methods are provided for depositing amorphous carbon materials. In one aspect, the invention provides a method for processing a substrate including positioning the substrate in a processing chamber, introducing a processing gas into the processing chamber, wherein the processing gas comprises a carrier gas, hydrogen, and one or more precursor compounds, generating a plasma of the processing gas by applying power from a dual-frequency RF source, and depositing an amorphous carbon layer on the substrate.

Abstract: Disclosed herein is a method of manufacturing semiconductor devices. The method includes the steps of forming a gate oxide film, a polysilicon film and a nitride film on a semiconductor substrate, and patterning the gate oxide film, the polysilicon film and the nitride film to form poly gates, forming a spacer at the side of the poly gate, forming a sacrifice nitride film on the entire surface, and then forming an interlayer insulation film on the entire surface, polishing the sacrifice nitride film formed on the interlayer insulation film and the poly gates so that the nitride film is exposed, removing top portions of the sacrifice nitride film while removing the nitride film, forming an insulation film spacer at the side exposed through removal of the nitride film, and filling a portion from which the sacrifice oxide film is removed with an insulation film, and forming the tungsten gates in portions from which the nitride films are moved.

Abstract: Interconnect metallization schemes and devices for flip chip bonding are disclosed and described. Metallization schemes include an adhesion layer, a diffusion barrier layer, a wetable layer, and a wetting stop layer. Various thicknesses and materials for use in the different layers are disclosed and are particularly useful for metallization in implantable electronic devices such as neural electrode arrays.

Abstract: A process for producing a tube suitable for microfluidic devices. The process uses first and second wafers, each having a substantially uniform doping level. The first wafer has a first portion into which a channel is etched partially therethrough between second and third portions of the first wafer. The first wafer is then bonded to the second wafer so that a first portion of the second wafer overlies the first portion of the first wafer and encloses the channel to define a passage. The second wafer is then thinned so that the first portion thereof defines a thinned wall of the passage. Second and third portions of the second wafer and part of the second and third portions of the first wafer are then removed, and the thinned wall defined by the second wafer is bonded to a substrate such that the passage projects over a recess in the substrate surface. The second and third portions of the first wafer are then removed to define a tube with a freestanding portion.

Abstract: The invention provides a method of growing a non-polar a-plane gallium nitride. In the method, first, an r-plane substrate is prepared. Then, a low-temperature nitride-based nucleation layer is deposited on the substrate. Finally, the non-polar a-plane gallium nitride is grown on the nucleation layer. In growing the non-polar a-plane gallium nitride, a gallium source is supplied at a flow rate of about 190 to 390 ?mol/min and the flow rate of a nitrogen source is set to produce a V/III ratio of about 770 to 2310.

Abstract: Plasma etch processes incorporating helium-based etch chemistries can remove dielectric a semiconductor applications. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate helium as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract: A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric material. The method for forming the structure includes forming an opening in an organic material, forming the high-k dielectric material and a conductive material within the opening and over the organic material then using chemical mechanical polishing to remove the high-k dielectric material and conductive material from regions outside the gate region.