Abstract: An insulating and capping structure of an integrated circuit is formed on a semiconductor wafer. An insulating layer is formed on the semiconductor wafer, and the insulating layer is comprised of a dielectric material having a low dielectric constant that is less than about 4.0 and having chemical bonds that are chemically reactive with a predetermined reactant. A reaction barrier layer is formed on the insulating layer, and the reaction barrier layer is comprised of a material that is not chemically reactive with the predetermined reactant. A capping layer is formed on the reaction barrier layer, and the capping layer is formed using the predetermined reactant.

Abstract: An anti-reflective coating for use in microcircuit fabrication and specifically using ultraviolet photolithographic processes. A three-layered anti-reflective coating is used to enhance metallization etching in the construction of microcircuits. The coating features a titanium nitride anti-reflective layer sandwiched between two titanium metal layers. The upper titanium layer protects subsequently applied deep ultraviolet photoresists from the deleterious effects of the titanium nitride anti-reflective layer. The unique character of the three layer anti-reflective coating allows the use of an efficient single chamber fabrication process to form the three-layer coating.

Abstract: A method of increasing the selectivity of silicon nitride deposition. A substrate is provided. A silicon oxide layer is formed over a portion of the substrate. Ammonia NH3 is passed over the silicon oxide layer and the substrate surface for a definite period to perform a surface treatment. Silicon nitride is subsequently deposited over the substrate and the silicon oxide layer.

Abstract: In the present invention, a diaphragm for pressurizing and heating an encapsulating material is pre-heated to a predetermined temperature before laminating a lamination unit comprising a photovoltaic module and the encapsulating material. As a result, one surface of the lamination unit is heated by a heater provided on a table and the other surface is heated by the diaphragm, so it is possible to prevent appearance of a temperature difference between the surfaces.

Abstract: Disclosed are a capacitor for a semiconductor memory device and a method of manufacturing the same. According to the present invention, the method includes the steps of: forming a lower electrode on a semiconductor substrate; nitride-treating the surface of the lower electrode so as to prevent a natural oxide layer from generating on the surface thereof; forming a Ta2O5 layer as a dielectric layer on the upper part of the lower electrode; forming a conductive barrier made of the silicon nitride layer on the upper part of the Ta2O5 layer; and forming an upper electrode on the upper part of the conductive barrier.

Abstract: A method for fabricating a ferroelectric device with improved ferroelectric characteristics and which can provide a reliable contact resistance of a barrier metal layer. The method includes forming an adhesion layer and a barrier metal layer to be electrically connected to the contact plug buried in an insulating layer. The adhesion layer and the barrier layer is then patterned to define an upper surface and a sidewall thereof. An oxidation barrier layer is formed on sidewalls of the patterned layer. An oxide electrode layer and a metal electrode layer are formed thereon for forming a lower electrode. Next, a ferroelectric film and an upper electrode layer are formed thereon. Subsequently, the upper electrode layer, ferroelectric film, platinum and the oxide electrode are patterned to form a ferroelectric capacitor. A diffusion barrier layer is then formed to protect the ferroelectric capacitor.

Abstract: Improved process for preparing vertical transistor structures in DRAMs, in which the trench top oxide separates the bottom storage capacitor from the switching transistor, and in which the upper part of the trench contains the vertical transistor at its side wall, to obtain homogeneous gate oxidation at all different crystal planes inside the trench so that homogeneous thickness is independent of crystal orientation comprising: a) subjecting a wafer trench side wall to ion bombardment for a period sufficient to generate an amorphous layer of oxide side wall; and b) heating the wafer resulting from step (a) in an oxidizing atmosphere to cause oxidation and recrystallization of the amorphous layer.

Abstract: A method of manufacturing an electrical interconnection of a semiconductor device produces an erosion protecting plug in a contact hole to protect a selected portion of an interlayer dielectric layer when the interlayer dielectric layer is being etched to form a recess for a conductive line. The contact hole is formed in the interlayer dielectric layer. The contact hole is filled with an organic material to form the erosion protecting plug. The organic material is a photoresist material or an organic polymer. A photoresist pattern is formed for exposing the erosion protecting plug and a portion of the interlayer dielectric layer adjacent to the erosion protecting plug. A recess which extends down to the contact hole is formed by etching the portion of the interlayer dielectric layer which is exposed by the photoresist pattern. The erosion protecting plug and the photoresist pattern are then removed. A conductive line filling the recess and a contact filling the contact hole are then formed.

Abstract: A method of manufacturing a V-shaped flash memory. The V-shaped stack gate is formed by implanting ions into a substrate to form a buried source line using a mask, and then forming a V-shaped trench that exposes the buried source line in the substrate. A V-shaped word line stack gate is next formed over the trench and the substrate next to the trench. A common drain terminal is formed in the substrate on each side of the V-shaped stack gate. The drain terminal is electrically connected to a bit line by forming a contact plug.

Abstract: An improved and novel semiconductor device including an amorphous carbon layer for improved adhesion of photoresist and method of fabrication. The device includes a substrate having a surface, a carbon layer formed on the surface of the substrate, and a resist layer formed on a surface of the carbon layer. The device is formed by providing a substrate having a surface, depositing a carbon layer on the surface of the substrate using plasma enhanced chemical vapor deposition (PECVD) or sputtering, and forming a resist layer on a surface of the carbon layer.

Abstract: A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.

Abstract: A method of decapsulating a packaged die includes removing packaging material from the bottom section of a die-containing package to expose a die pan, removing the die pan, removing material between the die pan and the bottom surface of the die, using the bottom surface of the die to determine a grind plane substantially parallel to the top surface of the die, and removing packaging material from the top section of the die-containing package to form a top surface substantially planar to the grind plane, preferably intersecting the wire bonds on the face of the die.

Abstract: Methods are designed to manufacture an epitaxial wafer wherein the formation of defects in an epitaxial layer is sufficiently suppressed even if the epitaxial wafer is prepared from a silicon single crystal which is grown while doped with nitrogen. Specifically, the methods are to grow an epitaxial layer on a wafer sliced from (1) a silicon single crystal wherein the oxygen concentration at an OSF ring region is 9×1017 atoms/cm3 or less, (2) a silicon single crystal wherein the inside diameter of an OSF ring region is located at a position which is 85% or more of the wafer diameter, and (3) a silicon single crystal doped with nitrogen at a concentration between 1×1012 atoms/cm3 or more and 1×1014 atoms/cm3 or less.

Abstract: A new class of fabrication methods for embedded distributed grating structures is claimed, together with optical devices which include such structures. These new methods are the only known approach to making defect-free high-dielectric contrast grating structures, which are smaller and more efficient than are conventional grating structures.

Abstract: An optical illumination system wherein an increased amount of light from a light source can reach a light valve, in which a luminous flux of the light source is irradiated upon a first lens array. The luminous flux having passed through the first lens array is introduced to the polarization conversion system provided immediately before a second lens array, and a luminous flux coming out from the polarization conversion system is introduced to the second lens array and then irradiated upon the light valve. The first lens array has an image forming position f which satisfies S<f<L where L is an optical path length of a longer one of optical paths of P polarized light and S polarized light decomposed from the luminous flux from the light source by the polarization conversion system and S is an optical path length of a shorter one of the optical paths.

Abstract: A contact opening to a silicon substrate within which a metal contact is to be formed is cleaned by soft sputter etch to clean the substrate surface and remove any residue which would interfere with formation of a continuous silicide layer across the contact region. Contact profile protrusion at the interface between two dielectrics forming the insulating material through which the contact opening is formed is also reduced by the soft sputter etch. A barrier is formed over the contact region utilizing two discrete deposition steps, preferably separated by an interval of time and employing different process parameters, to provide a shift in the grain boundaries between the two barrier layers, creating diffusion traps at grain discontinuities inhibiting the diffusion of metal through the barrier layer. Performance of the barrier layer in preventing junction spiking is thereby increased.

Abstract: A method for forming thin films on substrates wherein the films are produced by applying a solution of an electrically insulating, heat-curing resin onto the substrate, evaporating the solvent and exposing the resin to high energy radiation to cure the resin. The resin solution contains a substance selected from solvents and gas generating additives that causes the dedensification of the film during the cure of the resin. This results in a film having a dielectric constant of below 2.7. A semiconductor device is also disclosed as having an interconnect structure including at least one electrically conductive layer with an interposed insulating layer having a dielectric constant of less than 2.7 wherein the insulating layer is produced by the method described above.

Abstract: A ceria based abrasive is used in a chemical mechanical polishing operation at low polish pressure, and a predetermined pH range, to achieve high polish rates and good uniformity when planarizing layers formed from low dielectric constant materials, including but not limited to polymers. The distribution of ceria particle sizes in an exemplary slurry is bimodal and controlled. In a particular embodiment a polishing abrasive containing a controlled distribution of ceria particle sizes is used in a CMP polisher apparatus with a polishing pressure of approximately 3 psi and a pH of approximately 10.6 to planarize polymer films.

Abstract: An electronic device such as a semiconductor device, a method of manufacturing the same, and an apparatus for manufacturing the same, wherein by placing a ceramic substrate provided with a metallic thin film integrated into at least one selected from an upper surface and a lower surface of the ceramic substrate in its peripheral portion so as to extend both inside and outside a cavity of a mold for transfer molding, and positioning the metallic thin film in a position with which an upper mold and a lower mold of the mold come into contact, occurrence of cracks or breakage in the ceramic substrate is prevented by buffering the pressure applied to the ceramic substrate so as to prevent a distortion force from being caused even when the ceramic substrate is sandwiched and compressed between the upper mold and the lower mold.

Abstract: A method is proposed for bonding a BGA (Ball Grid Array) package to a circuit board without causing the collapsing of the BGA package against the circuit board. The proposed method is characterized in the use of two groups of solder balls of different reflow collapse degrees, which are arranged in an interspersed manner among each other in the ball grid array. In one embodiment, the first group of solder balls are homogenously made of a solder material of a specific melting point; and the second group of solder balls each include an outer portion and a core portion, with the outer portion having substantially the same melting point as the first group of solder balls, and the core portion being greater in melting point than the outer portion. In another embodiment, the second group of solder balls are greater in melting point than the first group of solder balls.