Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: A photodetector device and a process for manufacturing the same are described. The photodetector device comprises a doped semiconductor substrate; an intrinsic semiconductor material layer formed over the substrate, for absorbing incident light; an upper semiconductor material layer doped with the opposite type to the substrate, formed on a portion of the intrinsic semiconductor material layer to allow at least a portion of the incident light to directly enter the intrinsic semiconductor material layer; an upper electrode formed in a predetermined pattern on the upper semiconductor material layer, the upper electrode electrically connected to the upper semiconductor material layer; and a lower electrode electrically connected to the substrate, wherein a portion of the intrinsic semiconductor material layer constitutes at least a part of a photo-receiving surface.

Abstract: A new device and technique to realize an improved integrated circuit device incorporates an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.

Abstract: An interconnect line that is enclosed within electrically conductive material is disclosed. The interconnect line, which is useful for electrically connecting devices in an integrated circuit, is defined by an aluminum layer having a bottom surface covered by a titanium layer, a top surface covered by a titanium layer, and opposing side surfaces covered by discrete titanium layers. The encapsulation of the aluminum layer within the titanium layers substantially precludes void formation within the aluminum layer. The interconnect line also may be upon a contact plug that is in electrical communication with an active area in an underlying semiconductor substrate.

Abstract: A magnetic storage cell includes an active layer and a reference layer which is structured to minimize disruptions to magnetization in its active layer. The reference layer is structured so that a pair of its opposing edges overlap a pair of corresponding edges of the active layer. This may be used minimize the effects of demagnetization fields on the active layer. In addition, the reference layer may be thinned at its opposing edges to control the effects of coupling fields on the active layer and balance the demagnetization field.

Abstract: In an embodiment of the present invention, a method is provided of patterning PZT layers or BST layers. For example, a PZT layer or a BST layer is plasma etched through a high-temperature-compatible mask such as a titanium nitride (TiN) mask, using a plasma feed gas comprising as a primary etchant boron trichloride (BCl3) or silicon tetrachloride (SiCi4). Although BCl3 or SiCl4 may be used alone as the etchant plasma source gas, it is typically used in combination with an essentially inert gas. Preferably the essentially inert gas is argon. Other potential essentially inert gases which may be used include xenon, krypton, and helium. In some instances O2 or N2, or Cl2, or a combination thereof may be added to the primary etchant to increase the etch rate of PZT or BST relative to adjacent materials, such as the high-temperature-compatible masking material. A TiN masking material can easily be removed without damaging underlying oxides.