Abstract: Method and apparatus for enhancing performance of a storage device, such as a solid-state drive (SSD). In some embodiments, the storage device monitors a rate at which client I/O access commands are received from a client to transfer data with a non-volatile memory (NVM) of the storage device. A ratio of background access commands to the client I/O access commands is adjusted to maintain completion rates of the client I/O access commands at a predetermined level. The background access commands transfer data internally with the NVM to prepare the storage device to service the client I/O access commands, and can include internal reads and writes to carry out garbage collection and metadata map updates. The ratio may be adjusted by identifying a workload type subjected to the storage device by the client.

Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.

Abstract: Embodiments herein describe using software or firmware to manage the device capability list of a PCIe device. That is, rather than relying on pure hardware to advertise the capabilities of a PCIe device, the embodiments herein permit software or firmware executing on a processor in the PCIe device to manage read and write requests associated with discovering the capabilities of the device and configuring the device.

Abstract: An electronic device includes a bus driver and circuitry. The bus driver is coupled to a parallel bus including N data lines. The circuitry is configured to receive a data unit for transmission over the N data lines, to determine a first count indicative of a number of data bits in the data unit having a predefined value, and a second count indicative of a number of inverted data bits relative to corresponding bits in a previously transmitted data unit, to make a decision of whether to invert the data unit based on the first and second counts, depending on whether such inversion is expected to reduce power consumption of transmitting the data unit over the bus, to produce an output data unit by retaining or inverting the data unit based on the decision, and to transmit the output data unit over the data lines via the bus driver.

Abstract: A semiconductor device includes a first chip, a plurality of second chips, and a plurality of first signal lines. The first chip is electrically connected to a terminal group that receives a first signal from a host. The second chips are electrically connected to the first chip and are capable of outputting respective ready/busy signals. The ready/busy signals can be transferred through the first signal lines. Each of the second chips is respectively connected to the first chip through a corresponding first signal line among the plurality of first signal lines.

Abstract: A variable-resistance exercise machine with network communication for smart device control and brainwave entrainment, comprising an exercise machine with a plurality of moving surfaces, that each provide an independent degree of resistance to movement, a sensor that detects movement and provides output to a controller, a brainwave entrainment manager that selects a brainwave entrainment frequency based on the sensor output, and a controller that receives an input from a user device, changes the operation of the plurality of moving surfaces based on the input, and sends the brainwave entrainment frequency to the user device.

Abstract: An information input device includes: a communication interface configured to communicate with each of a first external apparatus that operates using a first operating system and a second external apparatus that operates using a second operating system; and a controller configured to operate in a first mode corresponding to a first driver used by the first external apparatus when transferring data to the first external apparatus, and operate in a second mode corresponding to a second driver different from the first driver and used by the second external apparatus when transferring data to the second external apparatus.

Abstract: Systems and methods for fast activation of slaves during wake up in an audio system allow a master device in an audio system such as a SOUNDWIRE audio system to send system and/or topology information to capable slave devices during a wake up window so that the slaves may start in an active mode rather than a safe mode. In the most recent proposed versions of SOUNDWIRE, there is a check PHY_Num phase. The systems for fast activation of slaves cause a negative differential line to be driven with an encoded signal by the master during a check PHY_Num phase where the encoded signal indicates a fast mode speed. Capable slaves may then begin in a fast mode rather than a safe (and slow) mode. Latency may be reduced by starting in a fast mode, which may improve the user's audio experience.

Abstract: The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

Abstract: A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

Abstract: The present disclosure relates to a method, an electronic device, and a computer program product for monitoring a storage system. For example, a method of monitoring a storage system is provided. This method may include setting a quota type of a folder to be monitored in the storage system to a monitored type. This method may further include acquiring quota monitoring data of which the quota type is the monitored type from a quota monitoring report associated with the storage system. In addition, this method may further include generating storage information of the folder based on the quota monitoring data. In this way, the time spent on monitoring the storage system can be shortened, the system resources can be saved, and ultimately, the user experience can be improved.

Abstract: An embodiment circuit comprises a plurality of processing units, a plurality of data memory banks configured to store data, and a plurality of coefficient memory banks configured to store twiddle factors for fast Fourier transform processing. The processing units are configured to fetch, at each of the FFT computation stages, input data from the data memory banks with a burst read memory transaction, fetch, at each of the FFT computation cycles, different twiddle factors in a respective set of the twiddle factors from different coefficient memory banks of the coefficient memory banks, process the input data and the set of twiddle factors to generate output data, and store, at each of the FFT computation stages, the output data into the data memory banks with a burst write memory transaction.

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to use information on a data input port or data input bus to determine a communication status of one or multiple secondary devices on the bus.

Abstract: A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.

Abstract: A system and method for evaluation, detection, conditioning, and treatment of neurological functioning and conditions which uses data obtained while a person is engaged in simultaneously in a range of primary physical tasks combined with defined types of associative activity, such as listening, reading, speaking, mathematics, logic puzzles, navigation of a virtual environment, recall of past stimuli, etc. The data from the physical and associative activities are combined to generate a composite functioning score visualization indicating the relative functioning of areas aspects of neurological functioning; including those in which deficiencies may be present, which are early indicators of possible neurological conditions. Through algorithmic recommendations combined with expert and user input, a conditioning regimen targeting neurological aspects of interest paired with periodic testing allows the user to track their progress in these areas over time.

Abstract: Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.

Abstract: Apparatus and methods for high-speed drivers are provided herein. In certain embodiments, a high-speed driver multiplexes two or more data streams. The high-speed driver is implemented with a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing. Driver amplitude control schemes are also disclosed in which a controllable driver includes a group of differential series source transistor (SST) driver slices that are connected in parallel with one another to drive a pair of output terminals, and a group of attenuator slices that are connected in parallel with one another across the pair of output terminals. Additionally, the controllable driver includes a control circuit that activates an attenuator slice for each SST driver slice that is decommissioned to provide output amplitude control.

Abstract: Provided is a method of packet processing, the method including receiving an input/output (IO) request from a host, selecting a drive corresponding to the IO request using a hashing algorithm or a round-robin technique, and establishing a connection between the host and the drive.

Abstract: A computer system, remote control monitoring system, and remote control monitoring method are provided to instantly provide the local display screen of the local computer to the remote computer for remote real-time display. The remote control monitoring system is arranged in the local computer and has a signal receiver and a remote controller. The signal receiver receives the video signal from the processor, executes the signal transforming process to generate the video signal in different standards. The remote controller executes a network compressing process on the transformed video signal to generate the network transportable video data, and transmits the data to the remote computer for displaying the corresponding remote display screen on the remote computer. The present disclosure enables the implementing of the out-of-band remote displaying.