Abstract: A disc array includes a plurality of disc drives each having a magnetic disc for storing information, and a drive controller for accessing information on the disc. The drive controller performs array support functions to support the disc array. The drive controllers in each disc drive are coupled to one another so that the drive controllers can communicate to perform array support functions in cooperation with one another. An array controller is coupled to the drive controllers and each of the plurality of disc drives to control overall operation of the disc drives to store and retrieve information from target locations on the magnetic discs in the disc drives.

Abstract: An apparatus determines if a bit of a word is stuck or unchanging. The apparatus inputs test words to be tested, a zero word indicating that all bits have been turned off and a ones word to indicate that all bits have been turned on. A series of logical AND and logical OR operation with the zero word and the ones word and an exclusive OR operation determines if the bit is unchanging.

Abstract: A method of testing synchronous dynamic random access memories (SDRAMs) having a pair of memory banks, comprised of writing data into a first of the pair of memory banks at a first clock speed that can be used by a tester, transferring the data at a second clock speed much higher than the first clock speed from the first of the pair of memory banks to a second of the pair of memory banks, and then reading the second of the pair of memory banks at the first clock speed to the tester.

Abstract: Testing of the operation of a radio in a base station of a wireless communication network may be achieved without removing the radio from service and without utilizing a separate test radio. Data concerning call processing activities are collected during wireless communications. A failure condition on an overhead or traffic channel of a radio is identified by suitably accessing the collected data, processing the data and then comparing the results to expected values.

Abstract: Primary and secondary data processing systems are coupled via a communication system. Data storage in both systems is provided by a log structured array (LSA) system that stores data in compressed form. Each time data are updated within LSA, the updated data are stored in a data storage location different from the original data. Selected data recorded in a primary data storage of the primary system is remote dual copied to the secondary system for congruent storage in a secondary data storage, such as for disaster recovery purposes. The primary systems creates a remote copying session. Within such remote copying session, a series of "pending write update" sessions are ESTABLISHED. All data updated within each pending write update session is a consistency group of data. Within each pending write update session update data are retentively stored in both the primary and secondary systems (such as in a non-volatile cache).

Abstract: In a speech decoding apparatus (100) supplied with an input speech signal (101) comprising successive blocks, each comprising a digital speech signal and an error detecting code signal, an error detector (8) detects an error in the digital speech signal by the error detecting code signal for each block to produce error detection pulses whenever the error detector detects the error. The error detector also produces the digital speech signals of the blocks. A speech decoder (9) decodes the digital speech signals of the blocks into an analog speech signal. A measuring circuit (102) measures, as a measured value, the number of the error detection pulses during a predetermined time interval. A comparator (15) compares the measured value with a reference value to produce a command signal when the measured value is greater than the reference value. A generator (12) generates an alarm signal in response to the command signal.

Abstract: A BIST clock driver for providing memory elements in a combinational and sequential logic circuit with a global clock signal during user mode and a test clock signal during testing. The clock driver also supplies clock signals to memory circuits that have clock inputs supplied by random logic. The clock driver supplies the random logic with a global clock signal. A clock multiplexor receives the generated clock and the test clock signal and provides the memory element with the generated clock signal during user mode and the test clock during testing of the memory element.

Abstract: A high performance transport layer checksum calculation unit and method is described for use in computer data communications systems which provides simultaneous general purpose data movement and checksum calculations. Data must be copied from the main memory of a computer in order to be transmitted and often a checksum must be calculated on the data for error detection purposes. The invention involves performing both of these tasks simultaneously thus requiring only one scan of the data memory. The checksum calculation method improves throughput capacity via a unique hardware architecture supporting delayed checksumming of packet segments. A net improvement for packets larger than a certain size is achieved via partial addition during DMA controlled memory access allowing improved average cycle time per data packet segment.

Abstract: In a disk drive where data bits containing a bit sequence signifying a specified location of a data block are read from a disk. A reference bit sequence identical to the recovered bit sequence is generated. Each of the recovered bit sequence and the reference bit sequence is divided into M groups of K bits. The M groups of the recovered bit sequence and the corresponding M groups of the reference bit sequence are compared with each other and a coincidence signal is produced for each of M pairs of compared groups when there is a bit-by-bit match therebetween. A match detector determines if the coincidence signal is generated from all pairs of the compared groups or from N out of M pairs of the compared groups.

Abstract: Bugs are identified within a subject program by embellishing the program with specifications that specify relationships between abstract components of objects of the program. The dependency specified by the specifications are compared with the dependencies provided within the code of the subject program to identify any missing dependencies between abstract components in the code. Any missing dependencies in the code point to errors within the subject program.

Abstract: A Communication Interface Box (CIB) enables bidirectional synchronous/asynchronous data transfer between external devices including data terminal equipment (DTE) and data communication equipment (DCE) and a personal computer by way of the parallel port of the personal computer. The CIB provides one or more input/output ports from the DCE and DTE for receiving or transmitting serial data. A bidirectional universal synchronous/asynchronous transmitter/receiver USART and a control circuit are used to transfer control and data signals between external devices and a personal computer for serial data analysis. The CIB eliminates the need for equipment dedicated solely to serial data analysis as well as the need to add hardware boards to personal computers to perform serial data analysis. The CIB allows for serial data analysis by way of the parallel port of a personal computer.

Abstract: To verify proper interconnection of an interconnect network, a transitory test signal is introduced at a first node of a network within a system under test. A search is made of all other system nodes for responsive transitions. A comparison is made between the addresses of nodes where transitions are observed within a predetermined time span and the addresses of nodes where transitions are expected. The predetermined time span is adjusted to detect missing or miswired line-conditioning components.

Abstract: The dynamically mapped data storage subsystem generates a two error correction, three error detection code of extent sufficient to cover not only the data but also the corresponding memory address for each data record stored therein. The error correction code is transmitted and stored with the data within the data storage subsystem to ensure the integrity of both the data and its memory address.

Abstract: An integrated circuit tester uses the information compared between a test executed result and an expected value, for the operation of a driver, which applies test patterns to a device under test. Once a test executed result obtained from the device is compared with an expected value, the compared information is fedback to the driver so as to specify, for example, test cycles and test patterns. Therefore, in an evaluation of maximum operating frequencies, the failure which occurs in the (n+1)th lower frequency can be effectively observed without being masked by other failures which occur in the nth lower frequency or less.

Abstract: A semiconductor integrated circuit includes a plurality of writable/readable memory blocks with different address spaces and an address decoder for selecting addresses of the memory blocks. The multiple memory blocks are permitted to share a part of addresses of the memory blocks in a test mode. The writing operation of one of the memory blocks that does not have the largest address space is disabled during a period in which address signals for commonly performing an address scan of individual memory blocks exceeds the address width of that memory block. It is therefore possible to permit a plurality of memory blocks with different address spaces mounted on the same chip to be tested with high precision and without additional burden on the generation of test vectors or on a BIST (built-in self test) test circuit.

Abstract: A method is provided for testing a non-programmable non-volatile memory which does not require the writing or erasing of any cells and permits the testing of all normal memory cells. Testing occurs from the device I/O pins and is useful in cases where EPROM memory cells have been bulk erased and placed within an ultraviolet-opaque package. The non-volatile memory is of the type having memory banks of rows and columns. Each bank must have address decoders and means for changing addresses between banks. A separate auxiliary cell or row of cells in a state different from the non-programmed state is provided. An address is supplied for the auxiliary cells and then for the normal cells and the interval between addressing the normal cells and the appearance of an output signal is measured and compared with a predetermined fixed limit. If the limit is exceeded, the address is identified as that of a weak cell whose speed does not meet product specifications.

Abstract: A maximum likelihood detector using the Viterbi algorithm for estimating a sequence of data bits received over a communication channel. Depending on the constraint length (C), a plurality of different states is associated with the transmitted bits (e.g. 16 if C=4). The detector comprises various data sources relating respectively to state transition probabilities (branch metrics, previous partial path metrics) and observed values of the received bits. Means are provided for calculating the partial path metrics for each state using values from said data sources. The calculating means comprise a common adder/accumulator for performing repeated additive arithmetic operations and for storing the cumulative result thereof. Multiplexing means are also provided for selectively coupling the data sources in a predetermined order to the adder/accumulator to implement the partial path metric calculation.

Abstract: A disk drive array data storage subsystem maps between virtual and physical data storage devices and schedules the writing of data to these devices. The data storage subsystem functions as a conventional large form factor disk drive memory, using a plurality of redundancy groups, each containing n+m disk drives. The use of a pool of r shared spare disk drives in this system is enhanced by apparatus which predicts the exhaustion of the pool of spare disk drives and automatically reorders additional disk drives to replace failed disk drives in the data storage subsystem. The spare disk drive replacement scheduling system records disk drive failure data and extrapolates past failure events to a target date at which the pool of spare disk drives will be exhausted. This exhaustion date is then modified by a reorder and restocking time interval indicative of the time it takes for a repairperson to be dispatched to replace the failed disk drives and replenish the pool of shared spare disk drives.

Abstract: A CRC operating unit which performs a CRC operation on received data using as an initial value a CRC operation result actual value obtained in a previous operation, and outputs a CRC operation result actual value. A delay unit delays the CRC operation result actual value by the time taken for a header part to be entered. The CRC operation result derivation unit outputs as a CRC operation result derivation value an operation result obtained by a CRC operation performed for all the receiving data of a header part provided with the above described CRC code using the CRC operation result actual value as an initial value. The coincidence detecting unit compares the CRC operation result actual value with the CRC operation result derivation value to detect the input timing of a header part as coincident timing for both values.

Abstract: An image processing system including a reconfiguration circuit, typically responding to fault detection. The image processing includes a data compressing unit for compressing image data generated by an image input terminal, a data storage unit for storing output compressed image data, a data decompressing unit for decompressing compressed data and for transferring the decompressed data to an output terminal. A control unit controls the system to compress and store image data, and then to repeatedly read out and transfer the stored data to the image output terminal. When a self diagnosis detects a fault in any one of the compressing unit, data storage unit, or data decompressing unit, the faulty unit is bypassed with a special data bus, thereby allowing system operating to continue.