Abstract: A system and method for testing first and second sets of electronic devices on a microchip is provided. The first set of devices receive input data and then send output data to a first multiple input shift register (MISR). The second set of devices receiving input data and then sending output data to a second MISR. The method includes determining a first seed signature value associated with the first MISR that induces the first MISR to have a first final signature value comprising a plurality of identical binary values when the first set of devices send valid output data to the first MISR when receiving a first predetermined sequence of input data.

Abstract: In a transmission network utilizing link fault protection between nodes, a working and a standby transmission line are terminated at each node with termination boards. The termination boards are adapted to report faults to a link supervision block. The link supervision block is adapted to switch between transmission lines in case of a fault. One or more persistency timers are coupled between the termination boards and the supervision block. A predetermined persistency period is applied to received fault cause(s) from the termination boards and correlated. The persistence of the correlation result is also timed and traffic is switched from one of the transmission lines to the other according to a predetermined correlation result persistency timer period.

Abstract: A soft-fust test algorithm is distributed on-chip from an ABSIT engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Using single-bit MISR error evaluation an ABSIT test sequence is executed concurrently on all arrays through the shift register chain. If any arrays are in error, redundancy compensation is employed and the ABIST test is repeated for all possible array redundant combinations until a functional configuration for each array is identified or all possible redundant combinations have been tried. Once functioning array configurations are verified, the associated soft-fuse states can be used to blow fuses and/or extracted for further system setup, permanent fuse-blowing and yield analysis. Multiple shift register chains driven by separate ABIST engines may be required to test all arrays on a chip.

Abstract: In one embodiment, a method provides scan patterns to an electronic device having BIST hardware. The BIST hardware has production and diagnostic test modes, and the device outputs one or more response signatures in the production test mode and outputs raw response data in the diagnostic test mode. In production test mode, the method uses ATE to 1) provide a first series of scan test patterns to the BIST hardware, and 2) capture and compare response signatures to expected response signatures, to identify a number of failing scan test patterns. The method then uses the ATE to identify a number of unique labels associated with the failing patterns. In diagnostic test mode, the method uses the ATE to 1) provide a second series of scan test patterns to the BIST hardware, and 2) capture raw response data. The scan test patterns in the second series correspond to the identified labels.

Abstract: A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for generating a first FBM. The redundant information is converted to a second FBM. The first and second FBMs are compared, thereby generating a third FBM according to comparison results.

Abstract: A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch. The full-scan latch has a test mode and a normal mode. When in the normal mode, the device operates as a transparent latch, passing a data input to its output. When in test mode, the device is operable to pass scan data down a scan chain and to inject scan data into the data path.

Abstract: Methods of error-tolerant modular testing of services are described, wherein an ordered list of test module identifiers is built in an error stack for the purposes of structured state teardown following the occurrence of an error during testing of services (i.e., network or other.) The error that triggers the teardown may comprise any error or more particularly an error not among a predetermined list of acceptable errors, the occurrence of which should not cause the cessation of services testing. Upon the occurrence of a triggering error, the test modules associated with the test module identifiers are executed in a reverse order to that which the test module identifiers were added to the error stack, effecting a structured state teardown.

Abstract: The present invention relates to a computer primary data storage system that integrates the functionality of file backup and remote replication to provide an integrated storage system that protects its data from loss related to system or network failures or the physical loss of a data center.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data stripe over an associated data channel. The plurality of data channels are organized into at least one group and each group has an associated parity channel to transmit a parity stripe generated based on the data stripes within the group. The apparatus also includes a reception module to receive the plurality of data stripes and the at least one parity stripe. The apparatus further includes a controller to control the operation of the apparatus.

Abstract: Methods and systems for testing devices in a scan chain are described. A first device for test and a second device for test are coupled in the scan chain. A signal selector is coupled between the first and second devices. The signal selector selects between an output signal that is output from the first device and a bypass signal that has bypassed the first device.

Abstract: A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” element to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.

Abstract: A DDR DRAM having a test mode and an operational mode and a method for testing the DDR DRAM. The method includes in the order recited: (a) placing the DDR DRAM in test mode; (b) issuing a band activate command to select and bring up a wordline selected for write of the DDR DRAM; (c) writing with auto-precharge, a test pattern to cells of the DDR DRAM; (d) repeating steps (b) and (c) until all wordlines for write have been selected; (e) issuing a bank activate command to select and bring up a wordline selected for read of the DDR DRAM; (f) reading with auto-precharge, the stored test pattern from cells of the DDR DRAM; and (g) repeating steps (c) and (f) until all wordlines for read have been selected.

Abstract: A memory testing apparatus rapidly tests memory devices with a relatively small error catch memory. The memory testing apparatus provides an address compressing module that minimizes an amount of error catch memory necessary to test one or more memory devices. The memory testing apparatus further divides each of the memory devices into a plurality of areas, and tests each area sequentially until a bit failure is detected in the area thereby attenuating testing time.

Abstract: A method of transmitting inband signaling messages in a mobile telecommunications network using SACCH burst. In order to avoid puncturing a fixed amount of bits out of every SACCH burst for inband signaling, the 40-bit FIRE code of the SACCH is replaced with a shorter CRC code, thereby creating unused bits for carrying the messages. After the SACCH block is shortened, a plurality of dummy bits are inserted into the shortened block prior to applying a ½ convolutional code to obtain the coded block. The coded block is further interleaved, reordered and mapped into 4 SACCH bursts. The dummy bits in each SACCH block are then replaced by the inband signaling for transmission.

Abstract: A content addressable memory (CAM) device having concurrent compare and error checking capability. The content addressable memory (CAM) device includes circuitry to compare a comparand with a plurality of data words stored within the CAM device in a compare operation, and circuitry to determine, concurrently with the compare operation, whether one of the data words has an error.

Abstract: A testing apparatus including a plurality of testing module slots to which different types of testing modules for testing a device under test are optionally mounted, includes a first and a second testing modules, and a synchronization controlling unit. The synchronization controlling unit includes an operation order holding unit for holding information indicating that a test operation by a first testing module should be performed before a test operation by a second testing module, a trigger return signal receiving unit for receiving a trigger return signal from the first testing module, and a trigger signal supplying unit for supplying a trigger signal to the second testing module, the trigger signal indicating that the second testing module should start the test operation thereof, when the trigger return signal receiving unit receives the trigger return signal.

Abstract: An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of the CAM locations that it is connected to in sequence. If an error is detected, the error detection and correction circuit rewrites the CAM location with the correct data. Multiple error correction and detection circuits can be used in the CAM device to test multiple CAM locations simultaneously.

Abstract: The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures are determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable.

Abstract: A recording and reproducing apparatus having an ECC-less error correction function, includes an erasure detector generating an erasure flag indicating erasure of a read signal; and an iterative decoder having two soft-in/soft-out (SISO) decoders, i.e., an inner decoder and an outer decoder, and correcting the erasure by inputting the erasure flag ek into the inner decoder and performing erasure compensation in the inner decoder. As the erasure compensation in the inner decoder, channel information is masked while the erasure flag is on. The erasure of data due to a media defect is detected inside the iterative decoder, and the second erasure flag is inputted into the inner decoder to perform erasure compensation in the inner decoder.

Abstract: A BIST architecture that allows efficient compression and application of deterministic ATPG patterns while tolerating uncertain bits is provided. In accordance with one feature of the invention, a large number of short scan chains can be configured between a decompressor and an observe selector. The observe selector selectively presents values of specific scan chains or scan cells to an external tester, thereby significantly reducing test data and test cycles. Advantageously, the core of the tested device is not changed as would be the case in BIST architectures including MISRs. Moreover, test points or logic to block uncertain bits do not need to be inserted. Furthermore, the loaded care bits for the scan chains as well as the bits for controlling the observe selector can be deterministically controlled, thereby providing optimal testing flexibility.