Abstract: There is disclosed, for use in a processing device having an N-way set associative data array (such as an L1 cache), a built-in self-test (BIST) circuit for testing the validity of storage locations in the data array. The BIST circuit comprises 1) a memory capable of storing a test program executable by the processing device, wherein the test program is capable of testing the validity of the storage locations in the data array; and 2) a controller capable of copying the test program from the memory into first selected storage locations in a first way in the data array, wherein the processing device executes the copied test program stored in the first selected storage locations subsequent to the copying to thereby test the validity of second selected storage locations in at least one of the N ways.

Abstract: The present invention provides a disk drive device containing a cache memory having K queue entries (K is an integer) to operate in a write cache mode and a method for controlling the disk drive device. The number of the queue entries to be used in the write cache mode can be gradually decreased from the number K to a decreased number by a predetermined number, and the number of the queue entries to be used in the write cache mode can be gradually increased from the decreased number towards the number K by a predetermined number, in response to values of parameters, such as an error rate and Non Repeatable Run Out or Repeatable Run Out of the rotating data recording disk at writing of data from the cache memory to a rotating data recording disk.

Abstract: An apparatus and method for controlling an asynchronous dual port FIFO memory is provided. The asynchronous FIFO may operate at frequencies satisfying 0.5f2<f1<f2 or 0.5f1<f2<f1, where f2 is the write frequency if f1 is the read frequency, or vice versa. A FIFO in accordance with the present invention comprises a dual port random access memory, a read pointer, a write pointer, a synchronization circuit and a status indicator. In the FIFO design, the read pointer indicating the read address is a simple sequential counter, and the write pointer indicating the write address is a Gray code counter. Gray code to sequential count converters are used to convert the Gray codes to sequential counts. The synchronization circuit synchronizes the write pointer and the read pointer using a read clock. A status indicator with simple circuits is provided to indicate if the FIFO is almost full or empty.

Abstract: Methods and apparatus for the efficient allocation of shared memory in a multi-threaded computer system are disclosed. In accordance with one embodiment of the present invention, a computer-implemented method for allocating memory shared by multiple threads in a multi-threaded computing system includes partitioning the shared memory into a plurality of blocks, and grouping the multiple threads into at least a first group and a second group. A selected block is allocated to a selected thread which may attempt to allocate an object in the selected block. The allocation of the selected block to the selected thread is based at least partially upon whether the selected thread is a part of the first group or the second group. In one embodiment, grouping the multiple threads into the first group and the second group includes identifying a particular thread and determining whether the particular thread is a fast allocating thread.