Patents Examined by Pierre-Michel Bataille
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Patent number: 11966622Abstract: A memory storage device that performs real-time monitoring is provided. The memory storage device comprises a memory controller, and a status indicating module/circuit, wherein the memory controller is configured to perform a first a second initialization operation, the first and second initialization operations performed in response to turning-on of the memory storage device, to generate a first status parameter regarding a status of the memory storage device in which the first initialization operation is performed, and to generate a second status parameter regarding the status of the memory storage device in which a second initialization operation is performed. The status indicating circuit includes a first transistor configured to operate on the basis of the first status parameter, a first resistor connected to the first transistor, a second transistor configured to operate on the basis of the second status parameter, and a second resistor connected to the second transistor.Type: GrantFiled: March 9, 2022Date of Patent: April 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Sung Oh Huh, Jong Kyu Choi, Soo-Hyeong Kim, Dong Hee Kim, Young San Kang
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Patent number: 11960407Abstract: Purging resources from a cache in a distributed networked system is described. A first data center of the distributed networked system receives a purge request to purge a resource from cache. If the purge request does not include a cache key, the first data center determines whether the purge request is valid, and if valid, purges the resource from cache of the first data center, generates a cache key for the resource, and causes the purge request that includes the generated cache key to be sent to other data centers of the distributed networked system for purging the resource from cache. If the purge request includes a cache key, the first data center skips determining whether the purge request is valid and purges the resource from cache based on the cache key.Type: GrantFiled: October 6, 2023Date of Patent: April 16, 2024Assignee: CLOUDFLARE, INC.Inventors: Zaidoon Abd Al Hadi, Connor Harwood, Alex Krivit, Samantha Aki Shugaeva, Steven Alexander Siloti
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Patent number: 11960722Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.Type: GrantFiled: July 25, 2022Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventors: Tomoharu Tanaka, Huai-Yuan Tseng, Dung V. Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda, James Fitzpatrick, Dave Ebsen
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Patent number: 11954341Abstract: A data storage system includes a plurality of data storage drives, and a system controller coupled to each data storage drive of the plurality of data storage drives. The system controller is configured to store internal drive management data for each data storage drive of the plurality of data storage drives.Type: GrantFiled: May 5, 2022Date of Patent: April 9, 2024Assignee: SEAGATE TECHNOLOGY LLCInventors: Jin Quan Shen, Xiong Liu, David W. Miller, Choonwei Ng
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Patent number: 11921638Abstract: According to some embodiments of the present invention, there is provided a hybrid cache memory for a processing device having a host processor, the hybrid cache memory comprising: a high bandwidth memory (HBM) configured to store host data; a non-volatile memory (NVM) physically integrated with the HBM in a same package and configured to store a copy of the host data at the HBM; and a cache controller configured to be in bi-directional communication with the host processor, and to manage data transfer between the HBM and NVM and, in response to a command received from the host processor, to manage data transfer between the hybrid cache memory and the host processor.Type: GrantFiled: June 6, 2022Date of Patent: March 5, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Krishna T. Malladi, Hongzhong Zheng
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Patent number: 11914865Abstract: A method and system are provided for limiting unnecessary data traffic on the data busses connecting the various levels of system memory. Some embodiments may include processing an invalidation command associated with a system or network operation requiring temporary storage of data in a local memory area. The invalidation command may comprise a memory location indicator capable of identifying the physical addresses of the associated data in the local memory area. Some embodiments may preclude the data associated with the system or network operation from being written to a main memory by invalidating the memory locations holding the temporary data once the system or network operation has finished utilizing the local memory area.Type: GrantFiled: April 11, 2022Date of Patent: February 27, 2024Assignee: Mellanox Technologies, Ltd.Inventors: Yamin Friedman, Idan Burstein, Hillel Chapman, Gal Yefet
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Patent number: 11914517Abstract: Methods and apparatus provide monitoring of memory access traffic in a data processing system by tracking, such as by data fabric hardware control logic, a number of cache line accesses to a page of memory associated with one or more memory devices, and producing spike indication data that indicates a spike in cache line accesses to a given page of memory. Pages are moved from a slower memory to a faster memory based on the spike indication data. In some implementations, the tracking is done by updating a cache directory with data representing the tracked number of cache line accesses.Type: GrantFiled: November 11, 2020Date of Patent: February 27, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Sergey Blagodurov, Marko Scrbak, Brandon K. Potter
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Patent number: 11893277Abstract: A data storage device is disclosed comprising a head actuated over a disk, a first semiconductor memory (SM) having a first endurance, and a second SM having a second endurance lower than the first endurance. A write command is received from a host including write data. When a size of the write command is less than a threshold, the write data is stored in a first SM write cache in the first SM, and when the size of the write command is greater than the threshold, the write data is stored in a second SM write cache in the second SM.Type: GrantFiled: February 20, 2021Date of Patent: February 6, 2024Assignee: Western Digital Technologies, Inc.Inventor: David R. Hall
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Patent number: 11893249Abstract: The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.Type: GrantFiled: March 9, 2022Date of Patent: February 6, 2024Assignee: Ceremorphic, Inc.Inventors: Subba Reddy Kallam, Partha Sarathy Murali, Venkata Siva Prasad Pulagam, Anusha Biyyani, Venkatesh Vinjamuri, Shahabuddin Mohammed, Rahul Kumar Gurram, Akhil Soni
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Patent number: 11886345Abstract: Configuring an address-to-SC unit (A2SU) of each of a plurality of CPU chips based on a number of valid SC chips in the computer system is disclosed. The A2SU is configured to correlate each of a plurality of memory addresses with a respective one of the valid SC chips. In response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips; while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips; and in response to reconfiguring the A2SU, resuming operation of the computer system.Type: GrantFiled: August 16, 2022Date of Patent: January 30, 2024Assignee: International Business Machines CorporationInventor: Burkhard Steinmacher-Burow
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Patent number: 11880678Abstract: A chip includes a power pin, a ground pin, a plurality of input/output (I/O) pins, a readable/writable memory, a switching circuit, and a control circuit. The I/O pins include a plurality of mapping pins and a control pin. The readable/writable memory includes a clock port, a plurality of I/O ports, and an enable port. The control circuit selectively activates or does not activate the switching circuit according to the control pin. When the switching circuit is activated, the switching circuit electrically couples the clock port, the I/O ports, and the enable port to the mapping pins respectively.Type: GrantFiled: December 10, 2020Date of Patent: January 23, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Neng-Hsien Lin, Wan-Pei Geng, Yao Feng, Chen Shen
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Patent number: 11874774Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.Type: GrantFiled: September 24, 2020Date of Patent: January 16, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Ravindra N. Bhargava, Ganesh Balakrishnan, Joe Sargunaraj, Chintan S. Patel, Girish Balaiah Aswathaiya, Vydhyanathan Kalyanasundharam
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Patent number: 11874776Abstract: Methods and apparatus relating to cryptographic protection of memory attached over interconnects are described. In an embodiment, memory stores data and a processor having execution circuitry executes an instruction to program an inline memory expansion logic and a host memory encryption logic with one or more cryptographic keys. The inline memory expansion logic encrypts the data to be written to the memory and decrypts encrypted data to be read from the memory. The memory is coupled to the processor via an interconnect endpoint of a system fabric. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 25, 2021Date of Patent: January 16, 2024Assignee: Intel CorporationInventors: Siddhartha Chhabra, Prashant Dewan
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Patent number: 11868273Abstract: Embodiments are directed to memory protection with hidden inline metadata to indicate data type and capabilities. An embodiment of a processor includes a processor core and cache memory. The processor core is to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata hidden at a linear address level, hidden from software, the hidden inline metadata to indicate data type or capabilities for the associated data stored on the same cacheline.Type: GrantFiled: June 29, 2019Date of Patent: January 9, 2024Assignee: Intel CorporationInventor: David M. Durham
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Patent number: 11868247Abstract: This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.Type: GrantFiled: March 21, 2023Date of Patent: January 9, 2024Assignee: Radian Memory Systems, Inc.Inventors: Andrey V. Kuzmin, James G. Wayda
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Patent number: 11861194Abstract: According to one embodiment, a storage device is configured to store unencrypted user data. The user data is erased according to at least one data erasure mechanism. The storage device comprises a receiver configured to receive an inquiry from a host device, and a transmitter configured to transfer response information indicating the at least one data erasure mechanism to the host device.Type: GrantFiled: May 3, 2022Date of Patent: January 2, 2024Assignee: Kioxia CorporationInventors: Hiroshi Isozaki, Teruji Yamakawa
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Patent number: 11853211Abstract: A data placement program causes a computer to execute a process of data placement in a main memory and a cache. When performing an operation using a first data groups and second data groups to generate pieces of operation result data representing operation results of the operation, based on a size of one piece of the operation result data and a size of an operation result area storing some of the plurality of pieces of operation result data in the cache memory, determining a number of the first data groups and a number of the second data groups, both corresponding to the some pieces of operation result data, and placing the plurality of first data groups and the plurality of second data groups in the main memory based on the determined number of the first data groups and the determined number of the second data groups.Type: GrantFiled: March 31, 2022Date of Patent: December 26, 2023Assignee: FUJITSU LIMITEDInventor: Yukihiro Komura
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Patent number: 11853593Abstract: Methods and systems for managing communications is disclosed. A host device and a management controller may communicate via memory mapped communications using shared memory. To improve the security of the memory mapped communications, access requests for shared memory may be monitored. Access controls for the shared memory may be put in place to reduce the likelihood of data being made unavailable before it is processed. The access controls may be lifted when the data stored in shared memory has been read by to complete the memory mapped communications.Type: GrantFiled: April 18, 2022Date of Patent: December 26, 2023Assignee: Dell Products L.P.Inventors: Bassem Elazzami, Adolfo Sandor Montero, Ibrahim Sayyed
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Patent number: 11847067Abstract: Methods and apparatus relating to cryptographic protection of memory attached over interconnects are described. In an embodiment, memory stores data and a processor having execution circuitry executes an instruction to program an inline memory expansion logic and a host memory encryption logic with one or more cryptographic keys. The inline memory expansion logic encrypts the data to be written to the memory and decrypts encrypted data to be read from the memory. The memory is coupled to the processor via an interconnect endpoint of a system fabric. Other embodiments are also disclosed and claimed.Type: GrantFiled: October 19, 2021Date of Patent: December 19, 2023Assignee: Intel CorporationInventors: Siddhartha Chhabra, Prashant Dewan
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Patent number: 11847054Abstract: A processing system server and methods for performing asynchronous data store operations. The server includes a processor which maintains a cache of objects in memory of the server. The processor executes an asynchronous computation to determine the value of an object. In response to receiving a request for the object occurring before the asynchronous computation has determined the value of the object, a value of the object is returned from the cache. In response to receiving a request for the object occurring after the asynchronous computation has determined the value of the object, a value of the object determined by the asynchronous computation is returned. The asynchronous computation may comprise at least one future, such as a ListenableFuture, or a process or thread. The asynchronous computation may determine the value of the object by querying at least one additional server.Type: GrantFiled: July 6, 2021Date of Patent: December 19, 2023Assignee: International Business Machines CorporationInventor: Arun Iyengar