Abstract: A method, system and computer program product for achieving activity centric computing. An activity (e.g., opening an application, opening an electronic communication, initiating a printing action, initiating a browsing session) performed by a user on a computing device is detected. In response to detecting the activity, the runtime environment is captured and the session workflow associated with the detected activity is recorded. The session workflow refers to the events performed by the user on the computing device in connection with performing an activity (e.g., application usage, web browsing) on the computing device. The captured runtime environment and the recorded session workflow associated with the detected activity are stored in a portable container. After receiving an indication to share the activity, an image of the container is created and stored in a repository to be shared among users to replay the session workflow associated with the activity.

Abstract: Technologies disclosed herein provide one example of a processor that includes a register to store a first encoded pointer for a first memory allocation for an application and circuitry coupled to memory. Size metadata is stored in first bits of the first encoded pointer and first memory address data associated with the first memory allocation is stored in second bits of the first encoded pointer. The circuitry is configured to determine a first memory address of a first marker region in the first memory allocation, obtain current data from the first marker region at the first memory address, compare the current data to a reference marker stored separately from the first memory allocation, and determine that the first memory allocation is in a first state in response to a determination that the current data corresponds to the reference marker.

Abstract: A method for operating a multi-transaction memory system, the method includes: storing Logical Block Address (LBA) information changed in response to a request from a host and a transaction identification (ID) of the request into one page of a memory block; and performing a transaction commit in response to a transaction commit request including the transaction ID from the host, wherein the performing of the transaction commit includes: changing a valid block bitmap in a controller of the multi-transaction memory system based on the LBA information.

Abstract: Indirect prefetch circuitry initiates a producer prefetch requesting return of producer data having a producer address and at least one consumer prefetch to request prefetching of consumer data having a consumer address derived from the producer data. A producer prefetch filter table stores producer filter entries indicative of previous producer addresses of previous producer prefetches. Initiation of a requested producer prefetch for producer data having a requested producer address is suppressed when a lookup of the producer prefetch filter table determines that the requested producer address hits against a producer filter entry of the table. The lookup of the producer prefetch filter table for the requested producer address depends on a subset of bits of the requested producer address including at least one bit which distinguishes different chunks of data within a same cache line.

Abstract: Methods, systems, and devices for advanced power off notification for managed memory are described. An apparatus may include a memory array comprising a plurality of memory cells and a controller coupled with the memory array. The controller may be configured to receive a notification indicating a transition from a first state of the memory array to a second state of the memory array. The notification may include a value, the value comprising a plurality of bits and corresponding to a minimum duration remaining until a power supply of the memory array is deactivated. The controller may also execute a plurality of operations according to an order determined based at least in part on a parameter associated with the memory array and receiving the notification comprising the value.

Abstract: An apparatus and method are provided for triggering action performance. One example apparatus comprises memory access circuitry to retrieve a data value from a memory location of a memory. The apparatus further comprises action triggering circuitry to determine whether the data value is to be interpreted according to a first interpretation or a second interpretation and, when it is determined that the data value is to be interpreted according to the second interpretation, determine whether the data value defines an action to be performed. When it is determined that the data value defines an action to be performed, the action triggering circuitry is to trigger performance of the action.

Abstract: Methods, systems, and devices for unmap operation techniques are described. A memory system may include a volatile memory device and a non-volatile memory device. The memory system may receive a set of unmap commands that each include a logical block address associated with unused data. The memory system may determine whether one or more parameters associated with the set of unmap commands satisfy a threshold. If the one or more parameters satisfy the threshold, the memory system may select a first procedure for performing the set of unmap commands different from a second procedure (e.g., a default procedure) for performing the set of unmap commands and may perform the set of unmap commands using the first procedure. If the one or more parameters do not satisfy the threshold, the memory system may perform the set of unmap commands using the second procedure.

Abstract: An illustrative method includes determining whether a virtual storage volume is successfully mounted to a mount path associated with a compute node, the mount path being marked as read-only, marking, if the determining includes determining that the virtual storage volume is successfully mounted to the mount path, the mount path as writable, and maintaining, if the determining includes determining that the virtual storage volume is unsuccessfully mounted to the mount path, the mount path as read-only.

Abstract: To generate sequential addresses when multiple integrated circuit (IC) devices are accessing a memory region, an address token is sent along the IC devices communicatively coupled in a ring topology. The address token includes a data increment value for the memory region. When a device receives the address token, a memory write address is determined based on the data increment value and a base address corresponding to the memory region for the current write cycle. The IC device can perform a write operation using the memory write address if the device has data to write. The data increment value of the address token is then updated based on the number of data units being written in the current write cycle to the memory region by the IC device, and the updated address token is transmitted to the next IC device of the ring topology.

Abstract: A memory controller includes a map buffer and a map update controller. The map buffer includes storage areas that respectively correspond to one or more indices. The map update controller stores metadata in a storage area corresponding to a target index among the one or more indices, and updates the metadata based on an update of mapping data for a first logical address. The metadata includes history information of a physical address mapped to the first logical address.

Abstract: Techniques are disclosed which allow a secondary storage system to provide data to non-production workloads in conjunction with performing data backup and protection tasks. As disclosed, a secondary storage system exposes backup data stored by the secondary storage system to other workloads, such as test and development applications, data analytics, etc. These non-production workloads can run at the same time the secondary storage system provides backup services to a primary storage system. This consolidation eliminates the need for an enterprise to deploy separate storage clusters for analytics, test and development applications, etc. and eliminates unnecessary copies of data.

Abstract: A computer-implemented method according to one aspect includes receiving a request to perform a transaction in persistent memory; determining a correlation between volatile memory address locations in a volatile transaction cache and persistent memory locations in the persistent memory; performing the transaction within the volatile memory address locations of the volatile transaction cache; identifying modified volatile memory address locations in the volatile transaction cache that have been written during the transaction; logging, within the persistent memory, data within the modified volatile memory address locations; copying the data within the modified volatile memory address locations to corresponding persistent memory locations in the persistent memory, utilizing the determined correlation; and removing the logged data from the persistent memory, in response to determining that the copying has completed.

Abstract: In a multi-node storage system, a node's capacity has an upper limit, and capacities provided by nodes are smaller than a capacity of a global pool. A volume having a capacity larger than the capacity of one node is created by the node. A write error occurs when an amount of data larger than the capacity of the node is written. A storage system reduces the frequency of such a write error. A global pool is based on a plurality of local pools of a plurality of storage nodes that constitute a node group. In any of the storage nodes, a capacity relationship is maintained where a used capacity of a volume created by the storage node is equal to or less than an available capacity of a local pool of the storage node. A storage management unit manages the node group and selects the storage node.

Abstract: The present technology includes a storage device including a memory device including a first storage region and a second storage region and a memory controller configured to, in response to a write request in the first storage region from an external host, acquire data stored the first region based on a fail prediction information provided from the memory device and to perform a write operation corresponding to the write request, wherein the first storage region and the second storage region are allocated according to logical addresses of data to be stored in by requests of the external host.

Abstract: A memory controller maintains a mapping of target ranges in system memory space interleaved two-ways across locations in a three-rank environment. For each range of the target ranges, the mapping comprises a two-way interleaving of the range across two ranks of the three-rank environment and offsets from base locations in the two ranks. At least one of the ranges has offsets that differ relative to each other. Such offsets allow the three ranks to be fully interleaved, two ways. An instruction to read data at a rank-agnostic location in the diverse-offset range causes the memory controller to map the rank-agnostic location to two interleaved locations offset different amounts from their respective base locations in their ranks. The controller may then affect the transfer of the data at the two interleaved locations.

Abstract: Data traffic comprising data packets communicated between a memory sub-system and a host system is monitored by a processing device at the memory sub-system. Data packets are classified according to packet type. Log data comprising a frequency and latency information associated with each packet type is generated. The log data is stored in a memory component of the memory sub-system.

Abstract: A logical-to-physical (L2P) address mapping table is maintained, wherein a plurality of sections of the L2P address mapping table is cached in a volatile memory device. A journal entry count is maintained reflecting a number of L2P journal entries associated with an L2P journal. It is determined that the journal entry count satisfies a first threshold criterion. In response to determining that the journal entry count satisfies the first threshold criterion, a writing of the L2P journal to a non-volatile memory device is triggered. A written journal count reflecting a number of L2P journals written to the non-volatile memory device is maintained. In response to determining that the written journal count satisfies a second threshold criterion, a first section of the plurality of sections of the L2P address mapping table is identified. The first section of the L2P address mapping table is written to the non-volatile memory device.

Abstract: A memory system for maintaining data consistency and an operation method thereof are provided. The operation method includes: receiving a first data in a first cache of a first memory from a processor; reading the first data from the first cache and writing the first data as a redo log into a log buffer of the first memory; writing the redo log from the log buffer into a memory controller of the processor; performing an in-memory copy in a second memory to copy a second data as an undo log, wherein the second data is an old version of the first data; and writing the redo log from the memory controller into the second memory for covering the second data by the redo log as a third data, wherein the redo log, the third data and the first data are the same.

Abstract: Disclosed deduplication techniques at a distributed data storage system guarantee that space reclamation will not affect deduplicated data integrity even without perfect synchronization between components. By understanding certain “behavioral” characteristics and schedule cadences of backup operations that generate backup copies received at the distributed data storage system, data blocks that are not re-written by subsequent backup copies are pro-actively aged, while promoting continued retention of data blocks that are re-written. An expiry scheme operates with block-level granularity. Each unique deduplicated data block is given an expiry timeframe based on the block's arrival time at the distributed data storage system (i.e., when a backup copy supplies the block) and further based on backup frequencies of the various virtual disks referencing a unique system-wide identifier of the block, which is based on the block's hash value. Communications between components are kept to an as-needed basis.

Abstract: A processing device in a memory sub-system assigns each of a plurality of memory units associated with one or more memory die of a memory device a unique address by which each of the plurality of memory units is identified. The processing device further sends a multi-unit status command to the memory device, the multi-unit status command specifying a subset of the plurality of memory units using corresponding unique addresses and receives a response to the multi-unit status command, the response comprising a multi-bit value comprising a plurality of bits, wherein each bit of the plurality of bits represents a status of one or more parameters of a plurality of parameters for a corresponding one of the plurality of memory units.