Patents Examined by Quinton Brasfield
  • Patent number: 11721669
    Abstract: A semiconductor package is provided including a first semiconductor chip stack and a second semiconductor chip stack that are adjacent to each other. The first semiconductor chip stack includes a plurality of first semiconductor chips and a plurality of first adhesive layers. The second semiconductor chip stack includes a plurality of second semiconductor chips and a plurality of second adhesive layers. Each of the first semiconductor chips includes a first cell region and a first scribe lane that surrounds the first cell region. Each of the second semiconductor chips includes a second cell region and a second scribe lane that surrounds the second cell region. An area of the first scribe lane is greater than an area of the second scribe lane. The plurality of first adhesive layers and the plurality of second adhesive layers have the same coefficient of thermal expansion.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 8, 2023
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Junyeong Heo, Jae-Eun Lee, Yeongkwon Ko, Donghoon Won
  • Patent number: 11678574
    Abstract: Provided is a compound of Chemical Formula 1: HAr-L1-L2-Ar1??Chemical Formula 1 wherein: HAr is a group of the following Chemical Formula A-1 or A-2; L1 and L2 are the same as or different from each other, and each independently is a direct bond, a substituted or unsubstituted monocyclic or polycyclic arylene group, or a substituted or unsubstituted monocyclic or polycyclic heteroarylene group; and Ar1 is a substituted or unsubstituted monocyclic or polycyclic aryl group, or a substituted or unsubstituted monocyclic or polycyclic heteroaryl group; wherein: R1 to R3 are the same as or different from each other, and each independently is a substituted or unsubstituted linear or branched alkyl group; and is a site bonding to L1 of Chemical Formula 1, and an organic light emitting device comprising the same.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: June 13, 2023
    Assignee: LG CHEM, LTD.
    Inventors: Jungoh Huh, Sung Kil Hong, Dong Uk Heo, Miyeon Han, Jae Tak Lee, Junghoon Yang, Heekyung Yun
  • Patent number: 11664369
    Abstract: A semiconductor device includes a semiconductor layer, a first conductor disposed on the semiconductor layer, a second conductor disposed on the semiconductor layer so as to be separated from the first conductor, a relay portion that is formed on the semiconductor layer so as to straddle the first conductor and the second conductor and that is made of a semiconductor having a first conductivity type region and a second conductivity type region, a first contact by which the first conductivity type region and the second conductivity type region are electrically connected to the first conductor, and a second contact that electrically connects the first conductivity type region of the relay portion and the second conductor together and that is insulated from the second conductivity type region.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 30, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Yusuke Kubo
  • Patent number: 11665961
    Abstract: The present specification relates to a hetero-cyclic compound represented by Chemical Formula 1, and an organic light emitting device comprising the same.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: May 30, 2023
    Assignee: LT MATERIALS CO., LTD.
    Inventors: Hyun-Ju La, Yu-Jin Heo, Won-Jang Jeong, Jin-Seok Choi, Dae-Hyuk Choi, Joo-Dong Lee
  • Patent number: 11651976
    Abstract: Optical packages and methods of fabrication are described. In an embodiment, a controller chip is embedded along with optical components, including a photodetector (PD) and one or more emitters, in a single package.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: May 16, 2023
    Assignee: Apple Inc.
    Inventors: Kishore N. Renjan, Bilal Mohamed Ibrahim Kani, Kyusang Kim, Manoj Vadeentavida, Pierpaolo Lupo, Prashanth S. Holenarsipur, Praveesh Chandran, Vinodh Babu, Yuta Kuboyama
  • Patent number: 11646143
    Abstract: Various devices are described (along with methods for making them), where the device has a tunnel barrier sandwiched between two magnetic layers (one of the magnetic layers functioning as a free layer and the other of the magnetic layers functioning as a reference layer). One magnetic layer underlies the tunnel barrier and the other magnetic layer overlies the tunnel barrier, thereby permitting spin-polarized current to pass across the magnetic layers and through the tunnel barrier. At least one of the magnetic layers includes a metal oxide sublayer (e.g., an MgO sublayer) sandwiched between magnetic material.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: May 9, 2023
    Assignee: International Business Machines Corporation
    Inventor: Aakash Pushp
  • Patent number: 11594597
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Cheng-Ta Wu, Po-Wei Liu, Yeur-Luen Tu, Yu-Chun Chang
  • Patent number: 11563002
    Abstract: A semiconductor device includes a first fin that protrudes from a substrate and extends in a first direction, a second fin that protrudes from the substrate and extends in the first direction, the first fin and the second fin being spaced apart, a gate line including a dummy gate electrode and a gate electrode, the dummy gate electrode at least partially covering the first fin, the gate electrode at least partially covering the second fin, the dummy gate electrode including different materials from the gate electrode, the gate line covering the first fin and the second fin, the gate line extending in a second direction different from the first direction, and a gate dielectric layer between the gate electrode and the second fin.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: January 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Woo Kim, Choelhwyi Bae, Yang Gyeom Kim, Sung Eun Kim, Sang Woo Pae, Hyun Chui Sagong
  • Patent number: 11545484
    Abstract: A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: January 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jui-Fa Lu, Chien-Nan Lin, Ching-Hua Yeh
  • Patent number: 11538733
    Abstract: An electronic device includes a metal member and a connected member. A metal connecting layer is provided between a lower-side surface of the metal member and an upper-side surface of the connected member, to connect the metal member and the connected member to each other. The metal connecting layer includes at least one of metal films, each of which is made of gold or gold alloy. A thickness of the metal connecting layer in an opposing area between the metal member and the connected member is smaller than a flatness of each of the lower-side surface and the upper-side surface. A rust-preventing film is formed on a side wall of the metal member in such a way that the rust-preventing film extends from an outer periphery of the metal connecting layer to a position away from the outer periphery by a predetermined distance.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: December 27, 2022
    Assignee: DENSO CORPORATION
    Inventor: Toshihiro Miyake
  • Patent number: 11532624
    Abstract: A semiconductor device may include a plurality of first active fins protruding from a substrate, each of the first active fins extending in a first direction; a second active fin protruding from the substrate; and a plurality of respective first fin-field effect transistors (finFETs) on the first active fins. Each of the first finFETs includes a first gate structure extending in a second direction perpendicular to the first direction, and the first gate structure includes a first gate insulation layer and a first gate electrode. The first finFETs are formed on a first region of the substrate and have a first metal oxide layer as the first gate insulation layer, and a second finFET is formed on the second active fin on a second region of the substrate, and the second finFET does not include a metal oxide layer, but includes a second gate insulation layer that has a bottom surface at the same plane as a bottom surface of the first metal oxide layer.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: December 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Seok Jo, Jae-Hyun Lee, Jong-Han Lee, Hong-Bae Park, Dong-Soo Lee
  • Patent number: 11527548
    Abstract: A semiconductor device comprises a semiconductor material extending through a stack of alternating levels of a conductive material and an insulative material, and a material comprising cerium oxide and at least another oxide adjacent to the semiconductor material. Related electronic systems and methods are also disclosed.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Haoyu Li, Everett A. McTeer, Christopher W. Petz, Yongjun J. Hu
  • Patent number: 11527724
    Abstract: The present disclosure provides a hole transporting material, a method for preparing the same, and an electroluminescent device. The hole transporting material includes a compound of formula (I): A series of the hole transport materials with suitable HOMO/LUMO energy levels are synthesized by using bridged dihydrophenazine as a basis and different functional groups. Such materials can be applied to an organic electroluminescent device to improve mobility of a hole transport layer and thus improve luminous efficiency of the organic electroluminescent device.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 13, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Jiajia Luo
  • Patent number: 11524970
    Abstract: Provided are a nitrogen-containing compound, an electronic element, and an electronic device, and relates to the technical field of organic materials. The nitrogen-containing compound is shown as formula I, and can reduce the working voltage of an electronic element, improve the efficiency of an OLED, and prolong the service life of an OLED.
    Type: Grant
    Filed: October 10, 2020
    Date of Patent: December 13, 2022
    Assignee: SHAANXI LIGHTE OPTOELECTRONICS MATERIAL CO., LTD.
    Inventors: Qiqi Nie, Chao Yu
  • Patent number: 11515197
    Abstract: A semiconductor device includes: a substrate; an ion-implanted silicon layer disposed in the substrate; a first insulator layer disposed over the ion-implanted silicon layer; an active device disposed over the first insulator layer; and a conductive via configured to penetrate the first insulator layer for coupling the ion-implanted silicon layer and the active device.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 11502134
    Abstract: This disclosure relates to reduced power consumption OLED displays at reduced cost for reduced information content applications, such as wearable displays. Image quality for wearable displays can be different than for high information content smart phone displays and TVs, where the wearable display has an architecture that in includes, for example, an all phosphorescent device and/or material system that may be fabricated at reduced cost. The reduced power consumption can facilitate wireless and solar charging.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 15, 2022
    Assignee: Universal Display Corporation
    Inventors: Michael Hack, Julia J. Brown, Michael Stuart Weaver, Woo-Young So
  • Patent number: 11476240
    Abstract: According to one embodiment, a semiconductor device includes a board, a first member, a first adhesive layer, a first electronic component, a second electronic component, and a resin. The board includes a first surface. The first member includes a second surface, and a third surface made of a material including a first organic material. The first adhesive layer adheres to the first surface and the second surface. The first electronic component is attached to the first surface, and embedded in the first adhesive layer. The resin in which the first member, the first adhesive layer, and the second electronic component embedded adheres to the first surface and the third surface.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 18, 2022
    Assignee: Kioxia Corporation
    Inventor: Mariko Oishi
  • Patent number: 11476322
    Abstract: A display device includes a base, an organic light-emitting element including a stacked structure that has a first electrode layer, an organic light-emitting layer, and a second electrode layer that are stacked in order on the base, a drive element that is provided on the base, and drives the organic light-emitting element, and an auxiliary electrode layer provided on the base, and including an end surface that is in contact with the second electrode layer.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 18, 2022
    Assignee: SONY CORPORATION
    Inventor: Tatsuya Matsumi
  • Patent number: 11476349
    Abstract: A method includes forming a first fin and a second fin over a substrate, depositing an isolation material surrounding the first and second fins, forming a gate structure along sidewalls and over upper surfaces of the first and second fins, recessing the first and second fins outside of the gate structure to form a first recess in the first fin and a second recess in the second fin, epitaxially growing a first source/drain material protruding from the first and second recesses, and epitaxially growing a second source/drain material on the first source/drain material, wherein the second source/drain material grows at a slower rate on outermost surfaces of opposite ends of the first source/drain material than on surfaces of the first source/drain material between the opposite ends of the first source/drain material, and wherein the second source/drain material has a higher doping concentration than the first source/drain material.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chieh Chang, Shahaji B. More, Cheng-Han Lee
  • Patent number: 11443996
    Abstract: A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: September 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Keith Edward Johnson, Christopher Daniel Manack, Salvatore Frank Pavone