Abstract: Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment, forming a first set of semiconductor fins vertically extending from a substrate, and forming a second set of semiconductor fins vertically extending from the substrate, the distance between the first set of fins and the second set of fins defines a length of a junction. Embodiments also include forming a first epitaxy layer on the substrate, and forming a second epitaxy layer atop a portion of the first epitaxy layer, wherein a PN junction is formed between the first epitaxy layer and the second epitaxy layer, wherein a length of the PN junction is defined by the first set of semiconductor fins and the second semiconductor fins. Embodiments include forming a first metal contact atop the first epitaxy layer, and forming a second metal contact atop the second epitaxy layer.

Abstract: Disclosed is an organic light emitting display device. The organic light emitting display device includes a first emission part between a first electrode and a second electrode, a second emission part on the first emission part, and a first charge generation layer and a second charge generation layer between the first emission part and the second emission part. The first emission part includes a first organic layer, and the second emission part includes a second organic layer. A first thickness includes the first emission part and the first charge generation layer, and a second thickness includes the second emission part and the second charge generation layer. The first thickness is equal to or greater than the second thickness.

Abstract: An image generator for use in a display device, the image generator comprising: a plurality of ILED array chips each comprising a plurality of ILED emitters and arranged in an array such that each of a plurality of pixels of the image generator comprises an ILED emitter from each of a plurality of adjacent ILED array chips. The total area of ILED emitter material may be less than 50% of the area of each pixel. The image generator may comprise secondary optics in optical communication with an output of the plurality of ILED emitters of an ILED array chip and configured to direct light from the ILED emitters towards an emission region of the associated pixel.

Abstract: An example provides a method for forming an apparatus including a substrate imprinted with a pattern for forming isolated device regions. A method may include imprinting an unpatterned area of a substrate with a pattern to form a patterned substrate having a plurality of recessed regions at a first level and a plurality of elevated regions at a second level, and depositing a first layer of conductive material over the patterned substrate with a plurality of breaks to form a plurality of bottom electrodes. The method may include depositing a layer of an active stack, with a second layer of conductive material, over the plurality of bottom electrodes to form a plurality of devices on the plurality of recessed regions isolated from each other by the plurality of elevated regions.

Abstract: The present disclosure provides a semiconductor chip. The semiconductor chip includes a switching element having a gate electrode, a first pad, and a second pad. The first control pad is electrically connected to the gate electrode and applied with a voltage controlling the switching element to switch on or switch off. The second control pad provides a current path of a control current flowing between the first control pad and the second control pad when the switching element is in a switch-on state. One of the first control pad or the second control pad includes two pad components and a remaining one of the first control pad or the second control pad is disposed between the two pad components of the one of the first control pad or the second control pad.

Abstract: Methods of forming capacitors include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities.

Abstract: A composition for forming a coating is provided including at least one oxysilane-containing polymer or oligomer having an oxysilane group and at least one other organic crosslinkable group; an endcapping agent; and a solvent. A coated substrate, wherein the substrate is a silicon wafer or coated silicon wafer, includes an organic planarization layer in contact with the substrate, a photoresist layer, and a middle layer positioned between the organic planarization layer and the photoresist layer. The middle layer is formed from a composition including at least one oxysilane-containing polymer or oligomer having an oxysilane group and at least one other organic crosslinkable group, an endcapping agent; and a solvent.

Abstract: The present invention disclosure proposes a TFT array panel includes a back-channel etching structure TFT having a semiconductor layer made from a tin-silicon oxide, a source, and a drain. Both of the source and the drain are arranged on and contact the semiconductor layer.

Abstract: Fermi filter field effect transistors having a Fermi filter between a source and a source contact, systems incorporating such transistors, and methods for forming them are discussed. Such transistors may include a channel between a source and a drain both having a first polarity and a Fermi filter between the source and a source contact such that the Fermi filter has a second polarity complementary to the first polarity.

Abstract: The present disclosure relates to a thin film transistor substrate having a color filter layer. The present disclosure provides a thin film transistor substrate comprising: a plurality of pixel areas disposed in a matrix manner on a substrate, each pixel area including an aperture area and a non-aperture area; a first color filter and a second color filter stacked at the non-aperture area on the substrate; an overcoat layer disposed on the first color filter and the second color filter; a semiconductor layer disposed at the non-aperture area on the overcoat layer; a gate insulating layer and a gate electrode stacked on a middle portion of the semiconductor layer; a third color filter at the non-aperture area on the semiconductor layer and the gate electrode; and a source electrode and a drain electrode disposed on the third color filter.

Abstract: Methods of forming semiconductor devices include forming a first dielectric layer over a semiconductor fin. A second dielectric layer is formed around the first dielectric layer. The semiconductor fin is recessed below a height of the first and second dielectric layers. Source and drain extensions are grown from the recessed semiconductor fin. The first dielectric layer is recessed to expose an underside of and sidewalls of the source/drain extensions. Conductive contacts are formed around exposed portions of the source/drain extensions.

Abstract: Disclosed is a liquid crystal display panel and a method for manufacturing the same. The panel includes a thin-film transistor. An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers. The active layer contacts with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.

Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.

Abstract: The present disclosure relates to a method for packaging an OLED display panel, an OLED display panel and an OLED display device. The method for packaging an OLED display panel comprises: providing a substrate and a cover plate, and forming a covering layer on the substrate, wherein the covering layer has a concave structure. The method further comprises forming another covering layer having a convex structure or forming an adhesive on the cover plate, wherein a bump of the convex structure or the adhesive may be accommodated in a recess of the concave structure.

Abstract: The purpose of the invention is to suppress image persistence. The structure if the invention is as follows: A liquid crystal display device comprising: scanning lines extending in a first direction and arranged in a second direction, video signal lines arranged to cross the scanning lines, a pixel area is surrounded by the scanning lines and the video signal lines, a pixel electrode is formed in the pixel area, wherein conductive wirings are formed over the video signal lines via an organic insulating film in a plan view in the display area where images are displayed, a width in the first direction of the conductive wiring is bigger than a width in the first direction of the video signal line, an amount that the conductive wiring protrude the video signal line in a plan view is essentially the same in both side of the video signal line.

Abstract: The present disclosure relates to a manufacturing method of array substrates, wherein a second masking process forming an active layer, a source electrode and a drain electrode further includes: forming a semiconductor thin-film layer, N+ doping thin-film layer, a metal thin-film layer, and a photo-resistor layer on a gate insulation layer in sequence; applying a gray-tone-mask process to expose and develop the photo-resistor layer to obtain a first photo-resistor mask; applying a first wet etching process and a first dry etching process to etch the metal thin-film layer, the semiconductor thin-film layer, and the N+ doping thin-film layer; applying a plasma ashing process to the first photo-resistor mask to obtain a second photo-resistor mask; applying a second wet etching process to etch the metal thin-film layer; and peeling off the second photo-resistor mask, applying a second dry etching process to etch the N+ doping thin-film layer.

Abstract: An LED package includes a substrate having a substrate main surface and a substrate back surface, which face opposite sides in a thickness direction, a main surface electrode which is disposed on the substrate main surface and includes a first pad and a first die pad separated from each other, a first LED chip which is mounted on the first die pad and has an electrode pad formed on a first chip main surface facing the same direction as the substrate main surface, and a first wire connecting the first pad and the electrode pad. The first pad has a first base portion and a first pad portion having one end connected to the first base portion. The first pad portion of the first pad extends from the first base portion toward the first die pad obliquely.

Abstract: A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

Abstract: Embodiments of the invention provide an array substrate. The array substrate comprises a plurality of pixel units. The array substrate comprises a first electrode layer, an insulating layer covering the first electrode layer, and a second electrode layer formed on the insulating layer. The first electrode layer comprises a first electrode arranged in each of the pixel units, the insulating layer comprises an insulating layer unit covering the surface of each of the first electrodes, and the second electrode layer comprises a second electrode arranged on the insulating layer unit. Within each of the pixel units, the insulating layer unit comprises a plurality of insulating regions, and at least one of the insulating regions has a dielectric constant different from dielectric constants of other insulating regions.

Abstract: A mount structure includes two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer at the interfaces with the two members. The bonding material layer contains a first intermetallic compound and a stress relaxation material. The first intermetallic compound has a spherical, a columnar, or an oval spherical shape, and the same crystalline structure as the first interface layer and the second interface layer, and partly closes the space between the first interface layer and the second interface layer. The stress relaxation material contains tin as a main component, and fills around the first intermetallic compound.