Patents Examined by R. Bruce Breneman
  • Patent number: 6171974
    Abstract: A plasma etch process for oxide having high selectivity to silicon is disclosed comprising the use of a mixture of SiF4 and one or more other fluorine-containing etch gases in an etch chamber maintained within a pressure range of from about 1 milliTorr to about 200 milliTorr. Preferably, the etch chamber also contains an exposed silicon surface. The plasma may be generated by a capacitive discharge type plasma generator, if pressures of at least about 50 milliTorr are used, but preferably the plasma is generated by an electromagnetically coupled plasma generator. The high selectivity exhibited by the etch process of the invention permits use of an electromagnetically coupled plasma generator which, in turn, permits operation of the etch process at reduced pressures of preferably from about 1 milliTorr to about 30 milliTorr resulting in the etching of vertical sidewall openings in the oxide layer.
    Type: Grant
    Filed: January 24, 1992
    Date of Patent: January 9, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey Marks, Jerry Yuen-Kui Wong, David W. Groechel, Peter R. Keswick, Chan-Lon Yang
  • Patent number: 6136711
    Abstract: A chemical mechanical polishing composition comprising a composition capable of etching tungsten and at least one inhibitor of tungsten etching and methods for using the composition to polish tungsten containing substrates.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: October 24, 2000
    Assignee: Cabot Corporation
    Inventors: Steven K. Grumbine, Christopher C. Streinz, Eric W.G. Hoglund
  • Patent number: 6112695
    Abstract: A gas inlet, which also serves as a counter electrode, is located inside of a vacuum chamber made of an electrically insulating material. A container is mounted on a mandrel mounted on the gas inlet. The chamber is evacuated to a subatmospheric pressure. A process gas is then introduced into the container through the gas inlet. The process gas is ionized by coupling RF power to a main electrode located adjacent an exterior surface of the chamber and to the gas inlet which deposits a plasma enhanced chemical vapor deposition (PECVD) thin film onto the interior surface of the container.
    Type: Grant
    Filed: October 8, 1996
    Date of Patent: September 5, 2000
    Assignee: Nano Scale Surface Systems, Inc.
    Inventor: John T. Felts
  • Patent number: 6110289
    Abstract: A novel rapid thermal process (RTP) barrel reactor processes a larger batch of semiconductor substrates than was previously possible. The RTP barrel reactor is characterized by a short process cycle time in comparison to the same process cycle time in a conventional CVD barrel reactor. A rapid heat-up of the substrates is one of the keys to the shorter process cycle times of the RTP barrel reactor. The RTP barrel reactor utilizes a radiant heat source in combination with a heat controller that includes an open-loop controller for heat-up and a closed-loop controller for deposition as well as a new energy stabilizer to achieve heating a larger energy stabilizer and volume to a uniform processing temperature in times characteristic of RTP reactors.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: August 29, 2000
    Assignee: Moore Epitaxial, Inc.
    Inventor: Gary M. Moore
  • Patent number: 6083419
    Abstract: A chemical mechanical polishing composition comprising a composition capable of etching tungsten and one inhibitor of tungsten etching and methods for using the composition to polish tungsten containing substrates.
    Type: Grant
    Filed: July 28, 1997
    Date of Patent: July 4, 2000
    Assignee: Cabot Corporation
    Inventors: Steven K. Grumbine, Christopher C. Streinz, Eric W. G. Hoglund
  • Patent number: 6079355
    Abstract: An electrode plate assembly for installation to an etching console includes a cooling electrode plate, an aligning peg, a covering plate and a plurality of screws for coupling the electrode cooling plate and cover plate. The cooling electrode plate is formed of a metallic, disk-shaped electrode plate including an aligning peg securing hole, a plurality of first screw holes and a plurality of first vent holes. The aligning peg is located within the aligning peg securing hole and protrudes from the cooling electrode plate. The covering plate is a thin disk-shaped plate including an aligning peg receiving hole, a plurality of second screw holes and a plurality of second vent holes. Upon installation, the covering plate and the cooling electrode plate are coupled by a plurality of screws through the first and second screw holes, with the aligning peg received in the aligning peg receiving hole of the covering plate to assure proper alignment of the plates.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: June 27, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chang Ping Lou, James Ho
  • Patent number: 6039835
    Abstract: A etcher (10) has an inner chamber (22) that is in communication with a collection chamber (17). A cover (33) is made from a substrate (11) and an outer housing (34). The cover (33) is attached to the etcher (10) so that the substrate (11) is suspended over the inner chamber (22). A recirculating system (29) is used to pass an etchant through a filter, into the inner chamber (22), across the substrate (11), into the collection chamber (17), and into a reservoir.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: March 21, 2000
    Assignee: Motorola, Inc.
    Inventors: Pawitter Jit Singh Mangat, Philip Armin Seese, William Joseph Dauksher
  • Patent number: 6030487
    Abstract: A wafer carrier assembly including a subassembly for in-situ nondestructive pad conditioning, characterized by continuously cleansing the pad surface with an energized fluid. The fluid may be abrasive in nature, such as a slurry, or non-abrasive, such as DeIonized (DI) water. In addition, the fluid may be of a type known to assist in removing slurry and/or residual materials from a pad surface and followed by a DI water rinse. The chemical may be either liquid or gas.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: February 29, 2000
    Assignee: International Business Machines Corporation
    Inventors: Thomas R. Fisher, Jr., Carol E. Gustafson, Michael F. Lofaro
  • Patent number: 6027602
    Abstract: An apparatus for wet processing of substrates in a controlled environment. It is a single-substrate processing apparatus which is capable of carrying out etching, rinsing, and drying processes all in a single apparatus and in a controlled environment. A closed processing chamber is provided for processing a substrate in a closed environment. Processing liquids and gases are introduced into the chamber and the chamber is rotated with the substrate. Temperature inside the chamber is controlled by heating the gases. Humidity is controlled by varying the proportion of water vapor. The rotation of the chamber with the substrate creates a stable environment where processing parameters are more easily controlled.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: February 22, 2000
    Assignee: Techpoint Pacific Singapore Pte. Ltd.
    Inventors: Ching-Chang Alex Hung, Ta-Hsing Fu
  • Patent number: 6024045
    Abstract: A method for treating the surface of a semiconductor layer includes the step of removing an oxide from the surface of a semiconductor layer by adding fluorine or fluoride to hydrogen radicals separately from plasma atmosphere and thereafter exposing the semiconductor layer to the mixed gas and hydrogen-terminating the surface.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: February 15, 2000
    Assignee: Fujitsu Limited
    Inventors: Jun Kikuchi, Shuzo Fujimura, Masao Iga
  • Patent number: 6016765
    Abstract: A plasma processing apparatus is furnished with a reactor which is furnished with a susceptor 12, a reaction gas delivery mechanism which delivers reaction gas to the inside of the reactor, a pumping mechanism 24 which pumps out an interior of the reactor, and a plasma-generating mechanism. The reactor is made of metal, the plasma-generating mechanism includes an at least single-winding coil 16 which produces an induced electric field, and the coil is established within the reactor and surrounding the plasma-generating space in a state surrounded by dielectrics parts 15 and 17.
    Type: Grant
    Filed: August 4, 1997
    Date of Patent: January 25, 2000
    Assignee: Anelva Corporation
    Inventors: Yoichiro Numasawa, Shinya Hasegawa, Tsutomu Tsukada, Nobuyuki Takahashi
  • Patent number: 6015463
    Abstract: A chemical vapor deposition system is provided. The chemical vapor deposition system is used to deposit an inorganic layer on a silicon wafer. The chemical vapor deposition system includes a reactor chamber, a particle trap, a gate valve, and a vacuum system. The vacuum system forces a gas out of the reactor chamber and through the particle trap and the gate valve. When the gate valve opens and closes, particles inside the valve can contaminate the reactor chamber and the vacuum system. The particle trap has a reservoir in which particles in the gas may become trapped before they reach the gate valve. The particle trap helps prevent the particles from becoming trapped in the gate valve.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: January 18, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Arthur Leo Cox
  • Patent number: 6012413
    Abstract: An electron beam source provides beam focusing by placing magnets under the crucible. The location of the magnets, operating in conjunction with the remaining magnetic and electromagnetic structure, permits varying sizes of crucibles to be used without redesign of the remainder of the electron beam source.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: January 11, 2000
    Assignee: MDC Vacuum Products Corp.
    Inventors: Nick Tsujimoto, Peter H. Harris, Wei Gao
  • Patent number: 6009828
    Abstract: A method for producing a thin semiconductor film according to the present invention includes the steps of: placing a group-IV compound or a derivative thereof in a plasma state; decomposing the group-IV compound or the derivative thereof into active species; and depositing the active species on a substrate, wherein energy for generating plasma is intermittently supplied at a supply time interval which is equal to or less than a reciprocal of {(secondary reaction rate constant of a source gas reacting with active species other than long-life active species within the plasma).times.(number of source gas molecules)}.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: January 4, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takashi Tomita, Katsuhiko Nomoto, Yoshihiro Yamamoto, Hitoshi Sannomiya, Sae Takagi
  • Patent number: 6008139
    Abstract: A method for etching metal silicide layers 22a, 22b and polysilicon layers 24a, 24b on a substrate 20 with high etching selectivity, and anisotropic etching properties, is described. In the method, the substrate 20 is placed in a plasma zone 55, and process gas comprising chlorine, oxygen and optionally helium gas, is introduced into the plasma zone. A plasma is formed from the process gas to etch the metal silicide layer 22 at high etching selectivity relative to etching of the polysilicon layer 24, while providing substantially anisotropic etching of the metal silicide and polysilicon layers. Preferably, the plasma is formed using combined inductive and capacitive plasma sources.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: December 28, 1999
    Assignee: Applied Materials Inc.
    Inventors: Shaoher Pan, Songlin Xu
  • Patent number: 6001184
    Abstract: This invention relates to an evaporation installation of the type including a frame rotatably hanging around a first vertical shaft and supporting at least three arms for receiving at least three concave supports of wafers to be processed, rotatably mounted around secondary shafts supported by the arms, the arms being inscribed in a cone which is coaxial to the first shaft so that the secondary shafts have a rotating motion in a plane perpendicular to the vertical shaft. The supports are disposed so as to overlap.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: December 14, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Franck Procureur
  • Patent number: 5993557
    Abstract: An apparatus for growing a high-quality single-crystalline semiconductor film on a substrate based on vapor phase growth while rotating the substrate and preventing micro-particles generated by a rotary drive unit from adhering onto the major plane of the substrate. The substrate 2 set inside the reaction chamber 21 is rotated using the rotary drive unit 7, a reaction gas 10 is fed to the major plane side of the substrate 2, a purge gas 3a is fed to the back space of the substrate in the reaction to chamber 21 to replace a space 11a with a carrier gas atmosphere, where the rotary drive unit 7 is located in the purge gas discharge section 13, a purge gas discharge duct 12 connected to the purge gas discharge section, and further to the purge gas discharge duct 12 is connected a gas flow controller 8, and serially in the downstream side thereof is connected an evacuation pump 9.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: November 30, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Munenori Tomita, Masanori Mayuzumi, Hitoshi Habuka
  • Patent number: 5989442
    Abstract: Method for wet etching where proper arrangements of the substrates during the growth of the insulation layer is adopted. An insulation layer is prepared on the surface of a substrate at the area where thin film circuits are positioned. On the surfaces of the substrate where the thin film circuits are not positioned are prepared protective layers. During the wet etching the attack by the etchant may be avoided. The material of the insulation layer and the protection layer may be the same. The material of the protection layer may be the photo-resistant used in the wet etching process. The invention also disclosed circuit components prepared with the wet etching of this invention.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: November 23, 1999
    Assignee: Industrial Technology Research Institute
    Inventors: Hsien-Fen Hsieh, Ming-Teh Hsu
  • Patent number: 5985035
    Abstract: In a method of holding a substrate and a substrate holding system, the amount of foreign substances on the back surface of the substrate can be decreased and only a small amount of foreign substances transferred from a mounting table to the substrate. For this purpose, the substrate holding system has a ring-shaped leakage-proof surface providing a smooth support surface on the specimen table corresponding to the periphery of the substrate, a plurality of contact holding portions which bear against the substrate on the specimen table between the corresponding position to the periphery of the substrate and the corresponding position to the center of the substrate, and electrostatic attraction means for fixing the substrate by contacting the back surface of the substrate to the ring-shaped leakage-proof surface and the contact holding portions.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: November 16, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Naoyuki Tamura, Kazue Takahashi, Youichi Ito, Yoshifumi Ogawa, Hiroyuki Shichida, Tsunehiko Tsubone
  • Patent number: 5976259
    Abstract: An improved semiconductor device manufacturing system and method is shown. In the system, undesirable sputtering effect can be averted by virtue of a combination of an ECR system and a CVD system. Prior to the deposition according to the above combination, a sub-layer can be pre-formed on a substrate in a reaction chamber and transported to another chamber in which deposition is made according to the combination without making contact with air, so that a junction thus formed has good characteristics.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: November 2, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki