Abstract: A ROM device includes cells with buried bit lines in a semiconductor substrate. A thin insulating layer covers the substrate has closely spaced, parallel, word lines formed thereon arranged orthogonally relative to the bit lines. The word lines are covered with reflowed glass insulating layers about 2500.ANG. thick. The glass insulating layers comprise a sublayer of undoped glass and an overlayer of doped glass, the underlayer about 500.ANG.-1500.ANG. thick and the overlayer about 1000.ANG.-1500.ANG. thick. An etched, patterned metal layer is formed on the glass insulating layer. The overlayer has been substantially removed by etching where the metal layer has been etched. An ion implantation pattern has been implanted into the substrate adjacent to the conductive lines. The device has been passivated. The implanted impurity ions having been activated by annealing the device.

Abstract: Hybrid power switching semiconductor devices advantageously integrate IGT and MOSFET structures. The IGT and MOSFET portions of the overall device include respective gate structures each having an associated gate electrode capacitance, and the hybrid device includes a resistance element connecting the IGT and MOSFET gates. The gate structures preferably comprise polysilicon electrodes, and the resistance element comprises a polysilicon bridge formed at the same time during device fabrication. The overall device has only a single gate terminal, which is connected relatively directly to one of the IGT and MOSFET gates, and indirectly through the resistance element to the other of the IGT and MOSFET gates such that an RC time delay network is defined. Two different types of power switching functions are achieved depending upon whether the overall device gate terminal is connected nearer the IGT gate or the MOSFET gate.

Abstract: A complementary type MOS field effect transistor circuit includes an input terminal, a P-MOS FET, an N-MOS FET connected in series with the P-MOS FET, a first resistor connected between the input terminal and the gate of the P-MOS FET, a second resistor connected between the input terminal and the gate of the N-MOS FET, a first diode connected between the gate of the P-MOS FET and a high voltage power supply terminal and a second diode connected between the gate of the N-MOS FET and a low voltage power supply terminal. The gate protection circuit of the circuit has a first part of the first resistor and the second diode and a second part of the second resistor and the second diode.

Abstract: A gate turn-off thyristor including N-type emitter regions (4) formed in part in the surface layer of a P-type base layer (3), and P.sup.+ layer regions (10) of a high impurity concentration formed immediately beneath gate electrodes (8) in the P-type base layer (3) and immediately beneath the periphery of the N-type emitter regions (4), such that the depth of the P.sup.+ layer regions immediately beneath the gate electrodes (8) is selected to be deeper than the N-type emitter regions (4).

Abstract: An enhanced mobility buried channel transistor structure in which the quasi-two-dimensional electron gas (2DEG) which forms the conducting channel in the structure is removed from the proximity of the heterointerface, and is placed in a region remote therefrom. A "tapered" layer of Al.sub.x Ga.sub.1-x As is provided, where x varies from maximum to minimum as the interface with an undoped layer of GaAs is approached.