Patents Examined by Ramamohan Rao Paladugu
  • Patent number: 5560776
    Abstract: A plasma discharge apparatus includes a chamber in which plasma discharge is produced; an antenna composed of a loop coil formed from an electric conductor which can be supplied with R.F. power so as to produce a high frequency electric field in the chamber; and an electric shield of a shield layer of non-magnetic electrically conductive material which toroidally surrounds the coil and which has openings. The shield layer is grounded and electrically connected to the antenna so as to be a return circuit. The electric shield can be formed from a strip electric conductor toroidally wound to provide a spiral gap opening between turns. The strip can further be toroidally wound over the spiral gap but separated from the underlying strip layer to form a double layer shield.
    Type: Grant
    Filed: September 9, 1994
    Date of Patent: October 1, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Sugai, Katsutaro Ichihara, Nobuaki Yasuda, Michiko Okubo
  • Patent number: 5560778
    Abstract: A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 1, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Seon Park, Myoung-Bum Lee, Chang-Gee Hong, Chang-Gyu Kim, U-In Chung
  • Patent number: 5559058
    Abstract: A method of growing a native oxide on a compound semiconductor material, comprising contacting the compound semiconductor material with an oxygen containing fluid, and pulsing a current between the compound semiconductor material the fluid, is presented. A "traveling oxide" can be produced when the oxygen containing fluid etches the native oxide. To obtain smooth oxides when the compound semiconductor material contains layers of different material, the oxide growth is monitored, and the pulse parameters changed in response to the monitoring of the oxide growth.
    Type: Grant
    Filed: November 15, 1994
    Date of Patent: September 24, 1996
    Assignee: Peter S. Zory, Jr.
    Inventors: Peter S. Zory, Jr., Douglas A. Hudson, Jr., Michael J. Grove
  • Patent number: 5556462
    Abstract: Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of integrated mass spectormeter (204) signals. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: September 17, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Francis G. Celii, Yung-Chung Kao, Andrew J. Purdes
  • Patent number: 5556804
    Abstract: A method of manufacturing a ridge-buried semiconductor laser includes growing semiconductor layers including at least a first conductivity type lower cladding layer, an active layer, and a second conductivity type upper cladding layer on a semiconductor substrate; forming a striped-shaped impurity diffusion source film including atoms producing the second conductivity type when diffused into the upper cladding layer at a stripe-shaped region which becomes a top of a ridge; ridge-etching the semiconductor crystal layers using a ridge-etching mask including the impurity diffusion source film so that the second conductivity type upper cladding layer has a ridge shape; growing a first conductivity type current blocking layer to bury the ridge; and forming a high dopant impurity concentration region including a dopant impurity producing the second conductivity type impurity in the second conductivity type upper cladding layer of the ridge region by diffusing atoms from the stripe-shaped impurity diffusion source f
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: September 17, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yutaka Nagai
  • Patent number: 5554559
    Abstract: A semiconductor device in which a capacitor (2) is provided on a surface (10) of a semiconductor body (3) with a semiconductor element (1) in which a lower electrode (11), an oxidic ferroelectric dielectric (12) and an upper electrode (13) are provided in that order, the upper electrode not covering an edge of the dielectric, after which an insulating layer (14) with superimposed metal conductor tracks is provided. According to the invention, the edge of the dielectric (12) not covered by the upper electrode (13) is coated with a coating layer (14, 20, or 30) practically imperviable to hydrogen, after which the device is heated in a hydrogen-containing atmosphere. Heating in a hydrogen atmosphere neutralizes dangling bonds which arise during deposition of the conductor tracks on the insulating layer, while the coating layer protects the dielectric from attacks by hydrogen. The semiconductor device then has a shorter access time.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: September 10, 1996
    Assignee: U.S. Philips Corporation
    Inventors: Robertus A. M. Wolters, Poul K. Larsen, Mathieu J. E. Ulenaers
  • Patent number: 5552345
    Abstract: Silicon on diamond die 5 are separated by patterning the diamond layer 3 and sawing the silicon layer 4. The diamond layer 3 is patterned by known techniques including laser ablation or using a silicon dioxide mask to resist deposition of diamond material. Patterning may take place after formation of microelectronic devices in dies in the silicon layer, after a device water is bonded to a diamond layer but before formation of the devices, prior to joining the device wafer to the diamond layer.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: September 3, 1996
    Assignee: Harris Corporation
    Inventors: Gregory A. Schrantz, Stephen J. Gaul, Jack H. Linn
  • Patent number: 5550081
    Abstract: By implementing oxidation to obtain a native oxide of aluminum (581,582) after a device has been metallized (505,565), advantages can be obtained in device operation, reliability, and life. A method of making a semiconductor device is disclosed and includes the following steps: forming a structure comprising layers of III-V semiconductor material, at least one of the layers being an aluminum-beating III-V semiconductor material (530,550); applying metal electrodes (505,565) to the structure to form a medalist semiconductor structure; and heating the medalist structure in a water-containing environment to convert a portion of the aluminum-bearing III-V semiconductor material to a native oxide of aluminum (581,582).
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: August 27, 1996
    Assignee: Board of Trustees Of The University Of Illinois
    Inventors: Nick Holonyak, Jr., Steven A. Maranowski, Fred A. Kish
  • Patent number: 5547899
    Abstract: In a method of making a semiconductor device, a p-type compound semiconductor layer containing zinc as a dopant impurity and including at least one transition metal element selected from the group consisting of Fe, V, Cr, Mn, Co, and Ni is grown on a second semiconductor layer, the at least one transition metal element inhibiting zinc from diffusing into the second semiconductor layer. A method of making a semiconductor laser includes growing the p-type compound semiconductor layer containing zinc as a cladding layer and the second layer is an undoped compound semiconductor active layer.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: August 20, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nariaki Fujii, Tatsuya Kimura
  • Patent number: 5543352
    Abstract: A method for manufacturing a thin film transistor having a crystalline silicon layer as an active layer comprises the steps of disposing a solution containing a catalyst for promoting a crystallization of silicon in contact with an amorphous silicon film, crystallizing the amorphous silicon at a relatively low temperature and then improving the crystallinity by irradiating the film with a laser light. The concentration of the catalyst in the crystallized silicon film can be controlled by controlling the concentration of the catalyst in the solution.
    Type: Grant
    Filed: November 16, 1994
    Date of Patent: August 6, 1996
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Corporation
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Hongyong Zhang, Naoaki Yamaguchi, Atsunori Suzuki
  • Patent number: 5543365
    Abstract: A channel is formed in a wafer to fore descrite die. A portion of the wafer is heated in the channel. A portion of the heated portion is cooled to eliminate the uniform structure. The cooled portion is scribed to separate the die.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: August 6, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Kendall S. Wills, Paul A. Rodriguez, Melvin Brewer
  • Patent number: 5543354
    Abstract: A semiconductor structure includes a first semiconductor barrier layer formed on a compound semiconductor substrate, a semiconductor carrier confinement layer formed on the semiconductor barrier layer, and a second semiconductor barrier layer arranged on the semiconductor carrier confinement layer. The semiconductor carrier confinement layer includes a plurality of islands spaced apart from each other and having an almost equal thickness, and a thin quantum well film arranged between the islands and having a thickness smaller than the thickness of the islands.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: August 6, 1996
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: N otzel Richard, Temmyo Jiro, Tamamura Toshiaki, Sugo Mitsuru, Kuramochi Eiichi, Nishiya Teruhiko
  • Patent number: 5540786
    Abstract: A novel photoluminescent material is disclosed comprising an active layer of ZnS.sub.1-x Te.sub.x deposited directly onto a substrate by molecular beam epitaxy. The emitted light is primarily in the blue end of the spectrum. The substrate may be GaAs or more preferably Si. Depositing the material directly onto Si allows the material to be used to manufacture integrated semiconductor light emitting devices. High efficiency may be obtained at low concentrations of Te (0.01.ltoreq.x.ltoreq.0.07) which allow good lattice matching of the active layer to an Si substrate.
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: July 30, 1996
    Assignee: The Hong Kong University of Science & Technology
    Inventors: Gui C. Xu, Iam K. Sou, Kam S. Wong, Hong Wang, Zhi U. Yang, George K. L. Wong
  • Patent number: 5540780
    Abstract: A temperature controlled source cell for use in the practice of thin film depositions by molecular beam epitaxy is described which includes an optical sensor for monitoring source temperature, the sensor including a light pipe having one end near the source and the other end coupled to a fiber optic probe which carries light from the light pipe to a remote optical detector.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: July 30, 1996
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Trice W. Haas, Kurt G. Eyink
  • Patent number: 5540783
    Abstract: A method and apparatus for digital epitaxy. The apparatus includes a pulsed gas delivery assembly that supplies gaseous material to a substrate to form an adsorption layer of the gaseous material on the substrate. Structure is provided for measuring the isothermal desorption spectrum of the growth surface to monitor the active sites which are available for adsorption. The vacuum chamber housing the substrate facilitates evacuation of the gaseous material from the area adjacent the substrate following exposure. In use, digital epitaxy is achieved by exposing a substrate to a pulse of gaseous material to form an adsorption layer of the material on the substrate. The active sites on the substrate are monitored during the formation of the adsorption layer to determine if all the active sites have been filled. Once the active sites have been filled on the growth surface of the substrate, the pulse of gaseous material is terminated. The unreacted portion of the gas pulse is evacuated by continuous pumping.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: July 30, 1996
    Assignee: Martin Marietta Energy Systems, Inc.
    Inventors: Djula Eres, Jeffrey W. Sharp
  • Patent number: 5532190
    Abstract: In the manufacture of a large-area electronic device such as a large-area liquid-crystal display device with thin-film address and drive circuitry, a plasma treatment is carried out on a device substrate (4) which is mounted on a supporting electrode (11) facing a perforated gas-feeding electrode (12). A reactive plasma (5) is generated in a space between the electrodes (11, 12) from a mixture of reaction gases which is fed into the space through at least the perforated electrode (12). The mixture of gases comprises a first reaction gas (e.g. SiH.sub.4) which is depleted at a faster rate in the plasma treatment than a second reaction gas (e.g N.sub.2). Through an area (12b) of the perforated electrode, one or more second supply lines (22) feeds a secondary mixture which is richer in the first reaction gas than a primary mixture supplied by a first supply line (21).
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: July 2, 1996
    Assignee: U.S. Philips Corporation
    Inventors: Andrew L. Goodyear, Ian D. French
  • Patent number: 5531835
    Abstract: A susceptor or other semiconductor wafer processing and/or transfer support platform includes a surface pattern having two or more regions of high and low elevation. The regions of high and low elevations can be rectangular/square dimpled patterns having tops coplanar with one another to support a semiconductor wafer for processing. The high and low regions can also be a wave form appearing to emanate from a point, where each of the wave crests form an imaginary plane on which a wafer to be processed can rest. The combination of high and low regions increases the average spacing between the wafer and the susceptor and reduces or eliminates the capacitive coupling (or sticking force) between processing hardware and a substrate (wafer) created by electrical fields during processing. The dimpled patterns are created by machining and can be created by using chemical and electrochemical etching of the wafer handling surfaces of processing hardware pieces.
    Type: Grant
    Filed: May 18, 1994
    Date of Patent: July 2, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Mark A. Fodor, Craig A. Bercaw, Charles Dornfest
  • Patent number: 5529952
    Abstract: A resonant tunneling diode (400) with lateral carrier transport through tunneling barriers (404, 408) grown as a refilling of trenches etched into a transverse quantum well (410) and defining a quantum wire or quantum dot (406). The fabrication method uses angled deposition to create overhangs at the top of openings which define sublithographic separations for tunneling barrier locations.
    Type: Grant
    Filed: September 20, 1994
    Date of Patent: June 25, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Bryan D. Smith, John N. Randall, Gary A. Frazier
  • Patent number: 5529949
    Abstract: Thin films of 2H .alpha.-silicon carbide are produced by pulsed laser ablation.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: June 25, 1996
    Assignee: Kent State University
    Inventors: Mark A. Stan, Martin O. Patton, Joseph D. Warner
  • Patent number: 5525538
    Abstract: An amorphous compound is changed to single crystal structure by heating at an elevated temperature in an inert atmosphere or in an atmosphere of a forming gas, the amorphous compound is composed of at least one Group III-A element of the Periodic Table and at least one Group V-A element, the amorphous compound having an excess over stoichiometric amount of at least one Group V-A element. The single crystal phase compound, intrinsically doped with at least one element from Group V-A, has the properties of high conductivity for a semiconductor without using any extrinsic dopant and a non-alloyed ohmic contact with a metal.
    Type: Grant
    Filed: March 8, 1995
    Date of Patent: June 11, 1996
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Mark E. Twigg, Mohammad Fatemi, Bijan Tadayon